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corrections to setvl from debugging
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 13 Mar 2021 16:08:39 +0000
(16:08 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 13 Mar 2021 16:08:39 +0000
(16:08 +0000)
openpower/isa/simplev.mdwn
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diff --git
a/openpower/isa/simplev.mdwn
b/openpower/isa/simplev.mdwn
index d283db9661bfd0776e2dbdcef046f09fe61050ab..350a2e89fc69c23710063661ec6c9c089e370ea6 100644
(file)
--- a/
openpower/isa/simplev.mdwn
+++ b/
openpower/isa/simplev.mdwn
@@
-9,22
+9,21
@@
Pseudo-code:
VLimm <- SVi + 1
if vs = 1 then
- if
RA
= 0 then
- VL <- (RA)[57:63]
+ if
_RA !
= 0 then
+ VL <- (RA
|0
)[57:63]
else
- VL <- VLimm[
2:8
]
+ VL <- VLimm[
1:7
]
else
VL <- SVSTATE[7:13]
if ms = 1 then
- MVL <- VLimm[
2:8
]
+ MVL <- VLimm[
1:7
]
else
MVL <- SVSTATE[0:6]
if VL > MVL then
VL = MVL
- SVSTATE[0:6] = MVL
- SVSTATE[7:13] = VL
- if RT != 0 then
- RT <- VL || [0] * 58
+ SVSTATE[0:6] <- MVL
+ SVSTATE[7:13] <- VL
+ RT <- [0]*57 || VL
Special Registers Altered: