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diff --git a/openpower/sv/microcontroller_power_isa_for_ai.mdwn b/openpower/sv/microcontroller_power_isa_for_ai.mdwn
index 15a13ade96ee82e1f3e0f36709879b00f7018565..0b09bff420b11a56756b6e656aaa5f5ce010a754 100644 (file)
--- a/openpower/sv/microcontroller_power_isa_for_ai.mdwn
+++ b/openpower/sv/microcontroller_power_isa_for_ai.mdwn
@@ -100,12 +100,11 @@ To achieve this requires some insights:
 
 2. If the Power ISA did not already have Carry-In/Out and Condition Registers, this entire idea would have much less merit.
 
-the idea of using multiple instructions to construct bigger integer values is nothing new, but doing so is far easier and more efficient if the ISA has Carry Flags.  that particularly hits home if the basic arithmetic width is only 8 or 16 bit!
+   the idea of using multiple instructions to construct bigger integer values is nothing new, but doing so is far easier and more efficient if the ISA has Carry Flags.  that particularly hits home if the basic arithmetic width is only 8 or 16 bit!
 
 3. SVP64 already has the concept of extending the GPRs and FPRs to 128 entries.  however if those are say 16 bit registers, the actual size of the regfile (in bytes) is back down to exactly the same size (in total bytes) as Power ISA 3.0
-
-  * only 32 16-bit registers would be alarmingly resource pressured, particularly given that 4 of them would be needed to construct a 64 bit LD/ST address
-  * 128 16-bit registers on the other hand are equivalent to 32 64-bit regs and Computer Science shows we are comfortable with that quantity.
+   - only 32 16-bit registers would be alarmingly resource pressured, particularly given that 4 of them would be needed to construct a 64 bit LD/ST address
+   - 128 16-bit registers on the other hand are equivalent to 32 64-bit regs and Computer Science shows we are comfortable with that quantity.
 
 4. Power ISA already has load-quad and store-quad which span 2
    registers: transparent seamless spanning of more than one