cpu: Style fixes in cpu/exec_context.hh and thread_context.hh.

Change-Id: I2eb82cc6f6ba29c1df74e53b78b57c1a65577837
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39659
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index c0b8dcd2fb693066edb8ad356bb88db0af74cac8..42dafbcacd7e7afd98ea8598f61915026b486ffc 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -105,36 +105,35 @@ class ExecContext
     /** Vector Register Interfaces. */
     /** @{ */
     /** Reads source vector register operand. */
-    virtual const TheISA::VecRegContainer&
-    readVecRegOperand(const StaticInst *si, int idx) const = 0;
+    virtual const TheISA::VecRegContainer& readVecRegOperand(
+            const StaticInst *si, int idx) const = 0;
 
     /** Gets destination vector register operand for modification. */
-    virtual TheISA::VecRegContainer&
-    getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
+    virtual TheISA::VecRegContainer& getWritableVecRegOperand(
+            const StaticInst *si, int idx) = 0;
 
     /** Sets a destination vector register operand to a value. */
-    virtual void
-    setVecRegOperand(const StaticInst *si, int idx,
-                     const TheISA::VecRegContainer& val) = 0;
+    virtual void setVecRegOperand(const StaticInst *si, int idx,
+            const TheISA::VecRegContainer& val) = 0;
     /** @} */
 
     /** Vector Register Lane Interfaces. */
     /** @{ */
     /** Reads source vector 8bit operand. */
-    virtual ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
+    virtual ConstVecLane8 readVec8BitLaneOperand(
+            const StaticInst *si, int idx) const = 0;
 
     /** Reads source vector 16bit operand. */
-    virtual ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
+    virtual ConstVecLane16 readVec16BitLaneOperand(
+            const StaticInst *si, int idx) const = 0;
 
     /** Reads source vector 32bit operand. */
-    virtual ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
+    virtual ConstVecLane32 readVec32BitLaneOperand(
+            const StaticInst *si, int idx) const = 0;
 
     /** Reads source vector 64bit operand. */
-    virtual ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
+    virtual ConstVecLane64 readVec64BitLaneOperand(
+            const StaticInst *si, int idx) const = 0;
 
     /** Write a lane of the destination vector operand. */
     /** @{ */
@@ -225,9 +224,9 @@ class ExecContext
      * mode need not override (though in that case this function
      * should never be called).
      */
-    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
-            Request::Flags flags,
-            const std::vector<bool>& byte_enable)
+    virtual Fault
+    readMem(Addr addr, uint8_t *data, unsigned int size,
+            Request::Flags flags, const std::vector<bool>& byte_enable)
     {
         panic("ExecContext::readMem() should be overridden\n");
     }
@@ -239,9 +238,9 @@ class ExecContext
      * mode need not override (though in that case this function
      * should never be called).
      */
-    virtual Fault initiateMemRead(Addr addr, unsigned int size,
-            Request::Flags flags,
-            const std::vector<bool>& byte_enable)
+    virtual Fault
+    initiateMemRead(Addr addr, unsigned int size,
+            Request::Flags flags, const std::vector<bool>& byte_enable)
     {
         panic("ExecContext::initiateMemRead() should be overridden\n");
     }
@@ -263,9 +262,9 @@ class ExecContext
      * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic
      * Read-Modify-Write Memory Operation)
      */
-    virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
-                         Request::Flags flags,
-                         AtomicOpFunctorPtr amo_op)
+    virtual Fault
+    amoMem(Addr addr, uint8_t *data, unsigned int size,
+            Request::Flags flags, AtomicOpFunctorPtr amo_op)
     {
         panic("ExecContext::amoMem() should be overridden\n");
     }
@@ -274,9 +273,9 @@ class ExecContext
      * For timing-mode contexts, initiate an atomic AMO (atomic
      * read-modify-write memory operation)
      */
-    virtual Fault initiateMemAMO(Addr addr, unsigned int size,
-                                 Request::Flags flags,
-                                 AtomicOpFunctorPtr amo_op)
+    virtual Fault
+    initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
+            AtomicOpFunctorPtr amo_op)
     {
         panic("ExecContext::initiateMemAMO() should be overridden\n");
     }

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 772a78039f4266d71c368fb8f4c47e619a0e7827..874146a55b2d3bb29d80bb2d404fe291f901020e 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -94,10 +94,7 @@ class ThreadContext : public PCEventScope
 
     bool getUseForClone() { return useForClone; }
 
-    void setUseForClone(bool newUseForClone)
-    {
-        useForClone = newUseForClone;
-    }
+    void setUseForClone(bool new_val) { useForClone = new_val; }
 
     enum Status
     {
@@ -288,7 +285,7 @@ class ThreadContext : public PCEventScope
 
     virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
 
-    virtual RegId flattenRegId(const RegId& regId) const = 0;
+    virtual RegId flattenRegId(const RegId& reg_id) const = 0;
 
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
@@ -332,8 +329,8 @@ class ThreadContext : public PCEventScope
             const TheISA::VecRegContainer& val) = 0;
 
     virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
-            const ElemIndex& elemIdx) const = 0;
-    virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
+            const ElemIndex& elem_idx) const = 0;
+    virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
             const TheISA::VecElem& val) = 0;
 
     virtual const TheISA::VecPredRegContainer &