The purpose of this RFC is to give a full list of the upcoming Scalar
opcodes developed by Libre-SOC, formally agree a priority order, which
ones should be EXT022 Sandbox, and for IBM to get a clear picture of
-the Opcode Allocation needs. Worth bearing in mind that every "Defined
+the Opcode Allocation needs. As this is a Formal ISA RFC the evaluation
+shall define (in advance of the actual submission of the instructions
+themselves) which instructions should be submitted over the next 18
+months.
+
+Worth bearing in mind during evaluation that every "Defined
Word" may or may not be Vectoriseable, but that every "Defined Word"
should have merits on its own not just when Vectorised. An example
of a borderline Vectoriseable Defined Word is `mv.swizzle` which
that lessons can be learned from other ISAs.
SVP64 Prefixing - also known by the terms "Zero-Overhead-Loop-Prefixing"
-as well as "True-Scalable Vector Prefixing" - also literally brings new
+as well as "True-Scalable-Vector Prefixing" - also literally brings new
dimensions to the Power ISA. Thus when adding new Scalar "Defined Words"
-it has to unavoidably be taken into consideration their value when
+it has to unavoidably and simultaneously be taken into consideration their value when
Vectorised.
+**Target areas**
+Whilst entirely general-purpose there are some categories that
+these instructions are targetting: Bitmanipulation, Big-integer,
+cryptography, Audio/Visual, High-Performance Compute, GPU workloads
+and DSP.
-Instruction count guide and approximate priority order:
+**Instruction count guide and approximate priority order**
* 6 - SVP64 Management [[ls008]] [[ls009]] [[ls010]]
* 5 - CR weirds [[sv/cr_int_predication]]