return nir;
}
+static void
+shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
+{
+ assert(glsl_type_is_vector_or_scalar(type));
+
+ uint32_t comp_size = glsl_type_is_boolean(type)
+ ? 4 : glsl_get_bit_size(type) / 8;
+ unsigned length = glsl_get_vector_elements(type);
+ *size = comp_size * length,
+ *align = comp_size * (length == 3 ? 4 : length);
+}
+
void
brw_nir_lower_resources(nir_shader *nir, struct gl_shader_program *shader_prog,
struct gl_program *prog,
NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo);
+ if (prog->nir->info.stage == MESA_SHADER_COMPUTE &&
+ shader_prog->data->spirv) {
+ NIR_PASS_V(prog->nir, nir_lower_vars_to_explicit_types,
+ nir_var_mem_shared, shared_type_info);
+ NIR_PASS_V(prog->nir, nir_lower_explicit_io,
+ nir_var_mem_shared, nir_address_format_32bit_offset);
+ }
+
NIR_PASS_V(prog->nir, gl_nir_lower_buffers, shader_prog);
/* Do a round of constant folding to clean up address calculations */
NIR_PASS_V(prog->nir, nir_opt_constant_folding);
const struct spirv_to_nir_options spirv_options = {
.environment = NIR_SPIRV_OPENGL,
- .lower_workgroup_access_to_offsets = true,
.frag_coord_is_sysval = ctx->Const.GLSLFragCoordIsSysVal,
.caps = ctx->Const.SpirVCapabilities,
.ubo_addr_format = nir_address_format_32bit_index_offset,