Merge pull request #1203 from whitequark/write_verilog-zero-width-values
authorClifford Wolf <clifford@clifford.at>
Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)
committerGitHub <noreply@github.com>
Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)
write_verilog: dump zero width constants correctly

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backends/verilog/verilog_backend.cc

Simple merge