vendor: don't emit duplicate iobuf submodule names.

These are no longer allowed after commit 698b005.

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index 843f8483b43cbf27c44d3bf1f30bef819a266617..b90e50efbebe30d9505c8f8b78455796636e28e5 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -272,7 +272,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("IB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -284,7 +284,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -296,7 +296,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OBZ",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -310,7 +310,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("BB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -324,7 +324,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("IB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
                 i_I=p_port[bit],
                 o_O=i[bit]
             )
@@ -336,7 +336,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
                 i_I=o[bit],
                 o_O=p_port[bit],
             )
@@ -348,7 +348,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OBZ",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit],
@@ -362,7 +362,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("BB",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 57d90e4735cec4020bb0f0f21e4e6599b200d9a1..ee6f5ce1bef0b068a799f5164a2a46faad14f5ff 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -253,9 +253,9 @@ class LatticeICE40Platform(TemplatedPlatform):
                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 
             if is_global_input:
-                m.submodules[pin.name] = Instance("SB_GB_IO", *io_args)
+                m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
             else:
-                m.submodules[pin.name] = Instance("SB_IO", *io_args)
+                m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)
 
     def get_input(self, pin, port, attrs, invert):
         self._check_feature("single-ended input", pin, attrs,

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 193221abb0798c993a69c1ee4fb91c8c1896fd9d..2fbcec5279b9db88f27651b078e4c3b48d740873 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -245,7 +245,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("IBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -257,7 +257,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -269,7 +269,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OBUFT",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -283,7 +283,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("IOBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -297,7 +297,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("IBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
                 i_I=p_port[bit], i_IB=n_port[bit],
                 o_O=i[bit]
             )
@@ -309,7 +309,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
             )
@@ -321,7 +321,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OBUFTDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
@@ -335,7 +335,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("IOBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 74a9645da1ffe2fd6129b23e93ad3ce5d678ccb1..754b2a97e0196eaacb238e29ec4e5bde050bb716 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -283,7 +283,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("IBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
                 i_I=port[bit],
                 o_O=i[bit]
             )
@@ -295,7 +295,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
                 i_I=o[bit],
                 o_O=port[bit]
             )
@@ -307,7 +307,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("OBUFT",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
                 i_T=t,
                 i_I=o[bit],
                 o_O=port[bit]
@@ -321,7 +321,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(port)):
-            m.submodules[pin.name] = Instance("IOBUF",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],
@@ -335,7 +335,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("IBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
                 i_I=p_port[bit], i_IB=n_port[bit],
                 o_O=i[bit]
             )
@@ -347,7 +347,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
             )
@@ -359,7 +359,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("OBUFTDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=p_port[bit], o_OB=n_port[bit]
@@ -373,7 +373,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
                                                o_invert=True if invert else None)
         for bit in range(len(p_port)):
-            m.submodules[pin.name] = Instance("IOBUFDS",
+            m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
                 i_T=t,
                 i_I=o[bit],
                 o_O=i[bit],