targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index bc5a673283cf948151fb68a76b79965d42dcdfed..9e4210b2599f05655c24a8ef86bfdd1a389a1aff 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -8,6 +8,7 @@ import argparse
 from migen import *
 
 from litex.boards.platforms import arty
+from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *
@@ -105,6 +106,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
     builder_args(parser)
     soc_sdram_args(parser)
+    vivado_build_args(parser)
     parser.add_argument("--with-ethernet", action="store_true",
                         help="enable Ethernet support")
     args = parser.parse_args()
@@ -112,7 +114,7 @@ def main():
     cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(**vivado_build_argdict(args))
 
 
 if __name__ == "__main__":