ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them...

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 2848763115d022a20060076726ab0420cc89d71c..d509fc28adca7e807dd536d05fe57be0135b4531 100644 (file)
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -328,6 +328,12 @@ let {{
                   case 1:
                     specReg = MISCREG_FPSCR;
                     break;
+                  case 6:
+                    specReg = MISCREG_MVFR1;
+                    break;
+                  case 7:
+                    specReg = MISCREG_MVFR0;
+                    break;
                   case 8:
                     specReg = MISCREG_FPEXC;
                     break;