nvc0: fixup gk110 and up not being listed in various switch statements
authorBen Skeggs <bskeggs@redhat.com>
Thu, 5 Dec 2013 23:09:42 +0000 (09:09 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 6 Dec 2013 01:28:45 +0000 (11:28 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/nouveau/nvc0/nve4_compute.c
src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c

index d65003ce4eb2a36fc41a6a789c2c9612fb196f64..bbf9838b1b44848b0d70092df39683ef532410cd 100644 (file)
@@ -851,6 +851,8 @@ GCRA::coalesce(ArrayList& insns)
    case 0xc0:
    case 0xd0:
    case 0xe0:
+   case 0xf0:
+   case 0x100:
       ret = doCoalesce(insns, JOIN_MASK_UNION);
       break;
    default:
@@ -1952,7 +1954,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
             texConstraintNVC0(tex);
             break;
          case 0xe0:
-         case NVISA_GK110_CHIPSET:
+         case 0xf0:
+         case 0x100:
             texConstraintNVE0(tex);
             break;
          default:
index 443acfcd8122bc7d0697ec87f1596e19b24ee968..112fca7d1529a50b707c9ac720ccc3cf780cb519 100644 (file)
@@ -134,11 +134,12 @@ extern Target *getTargetNV50(unsigned int chipset);
 
 Target *Target::create(unsigned int chipset)
 {
-   switch (chipset & 0xf0) {
+   switch (chipset & ~0xf) {
    case 0xc0:
    case 0xd0:
    case 0xe0:
-   case NVISA_GK110_CHIPSET:
+   case 0xf0:
+   case 0x100:
       return getTargetNVC0(chipset);
    case 0x50:
    case 0x80:
index 47e9c558d35025d88a5a9fe7c1f865111aec7cdd..1f3932ed7592f404115afc87e17de82654f53d5a 100644 (file)
@@ -46,12 +46,13 @@ TargetNVC0::TargetNVC0(unsigned int card) : Target(false, card >= 0xe4)
 void
 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
 {
-   switch (chipset & 0xf0) {
+   switch (chipset & ~0xf) {
    case 0xe0:
       *code = (const uint32_t *)&nve4_builtin_code[0];
       *size = sizeof(nve4_builtin_code);
       break;
    case 0xf0:
+   case 0x100:
       *code = (const uint32_t *)&nvf0_builtin_code[0];
       *size = sizeof(nvf0_builtin_code);
       break;
@@ -67,9 +68,12 @@ TargetNVC0::getBuiltinOffset(int builtin) const
 {
    assert(builtin < NVC0_BUILTIN_COUNT);
 
-   switch (chipset & 0xf0) {
-   case 0xe0: return nve4_builtin_offsets[builtin];
-   case 0xf0: return nvf0_builtin_offsets[builtin];
+   switch (chipset & ~0xf) {
+   case 0xe0:
+      return nve4_builtin_offsets[builtin];
+   case 0xf0:
+   case 0x100:
+      return nvf0_builtin_offsets[builtin];
    default:
       return nvc0_builtin_offsets[builtin];
    }
index b49f1aecfec344fb694f220160fabbc12ba1e001..ad287a2af6b694405108d5df1fe349671f1b4e31 100644 (file)
@@ -35,7 +35,7 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
    int ret;
    int i;
 
-   switch (dev->chipset & 0xf0) {
+   switch (dev->chipset & ~0xf) {
    case 0xc0:
       if (dev->chipset == 0xc8)
          obj_class = NVC8_COMPUTE_CLASS;
index 62ab2a276da2615a685af89068c54c16154db0cc..2c3a6978d585226efd45a8720b375c55191d257b 100644 (file)
@@ -478,7 +478,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
 {
    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 
-   switch (screen->base.device->chipset & 0xf0) {
+   switch (screen->base.device->chipset & ~0xf) {
    case 0xc0:
    case 0xd0:
       /* Using COMPUTE has weird effects on 3D state, we need to
@@ -489,6 +489,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
       return 0;
    case 0xe0:
    case 0xf0:
+   case 0x100:
       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
    default:
       return -1;
@@ -550,6 +551,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    case 0xd0:
    case 0xe0:
    case 0xf0:
+   case 0x100:
       break;
    default:
       return NULL;
@@ -597,7 +599,8 @@ nvc0_screen_create(struct nouveau_device *dev)
    screen->base.fence.emit = nvc0_screen_fence_emit;
    screen->base.fence.update = nvc0_screen_fence_update;
 
-   switch (dev->chipset & 0xf0) {
+   switch (dev->chipset & ~0xf) {
+   case 0x100:
    case 0xf0:
       obj_class = NVF0_P2MF_CLASS;
       break;
@@ -644,7 +647,8 @@ nvc0_screen_create(struct nouveau_device *dev)
    PUSH_DATAh(push, screen->fence.bo->offset + 16);
    PUSH_DATA (push, screen->fence.bo->offset + 16);
 
-   switch (dev->chipset & 0xf0) {
+   switch (dev->chipset & ~0xf) {
+   case 0x100:
    case 0xf0:
       obj_class = NVF0_3D_CLASS;
       break;
index 06c914fb5e63b20a6b25a95b00fbf475ed5840c5..f243316b899c76366b1d0af9bd9db48e4c9e5b17 100644 (file)
@@ -43,7 +43,8 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
    int ret;
    uint32_t obj_class;
 
-   switch (dev->chipset & 0xf0) {
+   switch (dev->chipset & ~0xf) {
+   case 0x100:
    case 0xf0:
       obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
       break;
index 7e88eae34450fea00df65371809e4315cce56c8e..e4f27f6cb249f159b191b942d630bc7f6bd0525d 100644 (file)
@@ -20,7 +20,7 @@ nouveau_drm_screen_create(int fd)
        if (ret)
                return NULL;
 
-       switch (dev->chipset & 0xf0) {
+       switch (dev->chipset & ~0xf) {
        case 0x30:
        case 0x40:
        case 0x60:
@@ -36,6 +36,7 @@ nouveau_drm_screen_create(int fd)
        case 0xd0:
        case 0xe0:
        case 0xf0:
+       case 0x100:
                init = nvc0_screen_create;
                break;
        default: