-/*\r
- * yosys -- Yosys Open SYnthesis Suite\r
- *\r
- * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\r
- * 2019 Eddie Hung <eddie@fpgeh.com>\r
- * 2019 David Shah <dave@ds0.me>\r
- *\r
- * Permission to use, copy, modify, and/or distribute this software for any\r
- * purpose with or without fee is hereby granted, provided that the above\r
- * copyright notice and this permission notice appear in all copies.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r
- *\r
- * ---\r
- *\r
- * Tech-mapping rules for decomposing arbitrarily-sized $mul cells\r
- * into an equivalent collection of smaller `DSP_NAME cells (with the \r
- * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached \r
- * to $shl and $add cells.\r
- *\r
- */\r
-\r
-`ifndef DSP_A_MAXWIDTH\r
-$fatal(1, "Macro DSP_A_MAXWIDTH must be defined");\r
-`endif\r
-`ifndef DSP_B_MAXWIDTH\r
-$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");\r
-`endif\r
-`ifndef DSP_B_MAXWIDTH\r
-$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");\r
-`endif\r
-`ifndef DSP_A_MAXWIDTH_PARTIAL\r
-`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH\r
-`endif\r
-`ifndef DSP_B_MAXWIDTH_PARTIAL\r
-`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH\r
-`endif\r
-\r
-`ifndef DSP_NAME\r
-$fatal(1, "Macro DSP_NAME must be defined");\r
-`endif\r
-\r
-`define MAX(a,b) (a > b ? a : b)\r
-`define MIN(a,b) (a < b ? a : b)\r
-\r
-(* techmap_celltype = "$mul $__mul" *)\r
-module _80_mul (A, B, Y);\r
- parameter A_SIGNED = 0;\r
- parameter B_SIGNED = 0;\r
- parameter A_WIDTH = 1;\r
- parameter B_WIDTH = 1;\r
- parameter Y_WIDTH = 1;\r
-\r
- (* force_downto *)\r
- input [A_WIDTH-1:0] A;\r
- (* force_downto *)\r
- input [B_WIDTH-1:0] B;\r
- (* force_downto *)\r
- output [Y_WIDTH-1:0] Y;\r
-\r
- parameter _TECHMAP_CELLTYPE_ = "";\r
-\r
- generate\r
- if (0) begin end\r
-`ifdef DSP_A_MINWIDTH\r
- else if (A_WIDTH < `DSP_A_MINWIDTH)\r
- wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-`ifdef DSP_B_MINWIDTH\r
- else if (B_WIDTH < `DSP_B_MINWIDTH)\r
- wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-`ifdef DSP_Y_MINWIDTH\r
- else if (Y_WIDTH < `DSP_Y_MINWIDTH)\r
- wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-`ifdef DSP_SIGNEDONLY\r
- else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)\r
- \$mul #(\r
- .A_SIGNED(1),\r
- .B_SIGNED(1),\r
- .A_WIDTH(A_WIDTH + 1),\r
- .B_WIDTH(B_WIDTH + 1),\r
- .Y_WIDTH(Y_WIDTH)\r
- ) _TECHMAP_REPLACE_ (\r
- .A({1'b0, A}),\r
- .B({1'b0, B}),\r
- .Y(Y)\r
- );\r
-`endif\r
- else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)\r
- \$mul #(\r
- .A_SIGNED(B_SIGNED),\r
- .B_SIGNED(A_SIGNED),\r
- .A_WIDTH(B_WIDTH),\r
- .B_WIDTH(A_WIDTH),\r
- .Y_WIDTH(Y_WIDTH)\r
- ) _TECHMAP_REPLACE_ (\r
- .A(B),\r
- .B(A),\r
- .Y(Y)\r
- );\r
- else begin\r
- wire [1023:0] _TECHMAP_DO_ = "proc; clean";\r
-\r
-`ifdef DSP_SIGNEDONLY\r
- localparam sign_headroom = 1;\r
-`else\r
- localparam sign_headroom = 0;\r
-`endif\r
-\r
- genvar i;\r
- if (A_WIDTH > `DSP_A_MAXWIDTH) begin\r
- localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\r
- localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);\r
- localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\r
- localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;\r
- if (A_SIGNED && B_SIGNED) begin : blk\r
- (* force_downto *)\r
- wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
- (* force_downto *)\r
- wire signed [last_Y_WIDTH-1:0] last_partial;\r
- (* force_downto *)\r
- wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
- end\r
- else begin : blk\r
- (* force_downto *)\r
- wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
- (* force_downto *)\r
- wire [last_Y_WIDTH-1:0] last_partial;\r
- (* force_downto *)\r
- wire [Y_WIDTH-1:0] partial_sum [n:0];\r
- end\r
-\r
- for (i = 0; i < n; i=i+1) begin:sliceA\r
- \$__mul #(\r
- .A_SIGNED(sign_headroom),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),\r
- .B_WIDTH(B_WIDTH),\r
- .Y_WIDTH(partial_Y_WIDTH)\r
- ) mul (\r
- .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),\r
- .B(B),\r
- .Y(blk.partial[i])\r
- );\r
- // TODO: Currently a 'cascade' approach to summing the partial\r
- // products is taken here, but a more efficient 'binary\r
- // reduction' approach also exists...\r
- if (i == 0)\r
- assign blk.partial_sum[i] = blk.partial[i];\r
- else\r
- assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\r
- end\r
-\r
- \$__mul #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(last_A_WIDTH),\r
- .B_WIDTH(B_WIDTH),\r
- .Y_WIDTH(last_Y_WIDTH)\r
- ) sliceA.last (\r
- .A(A[A_WIDTH-1 -: last_A_WIDTH]),\r
- .B(B),\r
- .Y(blk.last_partial)\r
- );\r
- assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\r
- assign Y = blk.partial_sum[n];\r
- end\r
- else if (B_WIDTH > `DSP_B_MAXWIDTH) begin\r
- localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
- localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);\r
- localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
- localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;\r
- if (A_SIGNED && B_SIGNED) begin : blk\r
- (* force_downto *)\r
- wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
- (* force_downto *)\r
- wire signed [last_Y_WIDTH-1:0] last_partial;\r
- (* force_downto *)\r
- wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
- end\r
- else begin : blk\r
- (* force_downto *)\r
- wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
- (* force_downto *)\r
- wire [last_Y_WIDTH-1:0] last_partial;\r
- (* force_downto *)\r
- wire [Y_WIDTH-1:0] partial_sum [n:0];\r
- end\r
-\r
- for (i = 0; i < n; i=i+1) begin:sliceB\r
- \$__mul #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(sign_headroom),\r
- .A_WIDTH(A_WIDTH),\r
- .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),\r
- .Y_WIDTH(partial_Y_WIDTH)\r
- ) mul (\r
- .A(A),\r
- .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),\r
- .Y(blk.partial[i])\r
- );\r
- // TODO: Currently a 'cascade' approach to summing the partial\r
- // products is taken here, but a more efficient 'binary\r
- // reduction' approach also exists...\r
- if (i == 0)\r
- assign blk.partial_sum[i] = blk.partial[i];\r
- else\r
- assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\r
- end\r
-\r
- \$__mul #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(A_WIDTH),\r
- .B_WIDTH(last_B_WIDTH),\r
- .Y_WIDTH(last_Y_WIDTH)\r
- ) mul_sliceB_last (\r
- .A(A),\r
- .B(B[B_WIDTH-1 -: last_B_WIDTH]),\r
- .Y(blk.last_partial)\r
- );\r
- assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\r
- assign Y = blk.partial_sum[n];\r
- end\r
- else begin\r
- if (A_SIGNED) begin : blkA\r
- wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\r
- end\r
- else begin : blkA\r
- wire [`DSP_A_MAXWIDTH-1:0] Aext = A;\r
- end\r
- if (B_SIGNED) begin : blkB\r
- wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);\r
- end\r
- else begin : blkB\r
- wire [`DSP_B_MAXWIDTH-1:0] Bext = B;\r
- end\r
-\r
- `DSP_NAME #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(`DSP_A_MAXWIDTH),\r
- .B_WIDTH(`DSP_B_MAXWIDTH),\r
- .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),\r
- ) _TECHMAP_REPLACE_ (\r
- .A(blkA.Aext),\r
- .B(blkB.Bext),\r
- .Y(Y)\r
- );\r
- end\r
- end\r
- endgenerate\r
-endmodule\r
-\r
-(* techmap_celltype = "$mul $__mul" *)\r
-module _90_soft_mul (A, B, Y);\r
- parameter A_SIGNED = 0;\r
- parameter B_SIGNED = 0;\r
- parameter A_WIDTH = 1;\r
- parameter B_WIDTH = 1;\r
- parameter Y_WIDTH = 1;\r
-\r
- (* force_downto *)\r
- input [A_WIDTH-1:0] A;\r
- (* force_downto *)\r
- input [B_WIDTH-1:0] B;\r
- (* force_downto *)\r
- output [Y_WIDTH-1:0] Y;\r
-\r
- // Indirection necessary since mapping\r
- // back to $mul will cause recursion\r
- generate\r
- if (A_SIGNED && !B_SIGNED)\r
- \$__soft_mul #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(1),\r
- .A_WIDTH(A_WIDTH),\r
- .B_WIDTH(B_WIDTH+1),\r
- .Y_WIDTH(Y_WIDTH)\r
- ) _TECHMAP_REPLACE_ (\r
- .A(A),\r
- .B({1'b0,B}),\r
- .Y(Y)\r
- );\r
- else if (!A_SIGNED && B_SIGNED)\r
- \$__soft_mul #(\r
- .A_SIGNED(1),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(A_WIDTH+1),\r
- .B_WIDTH(B_WIDTH),\r
- .Y_WIDTH(Y_WIDTH)\r
- ) _TECHMAP_REPLACE_ (\r
- .A({1'b0,A}),\r
- .B(B),\r
- .Y(Y)\r
- );\r
- else\r
- \$__soft_mul #(\r
- .A_SIGNED(A_SIGNED),\r
- .B_SIGNED(B_SIGNED),\r
- .A_WIDTH(A_WIDTH),\r
- .B_WIDTH(B_WIDTH),\r
- .Y_WIDTH(Y_WIDTH)\r
- ) _TECHMAP_REPLACE_ (\r
- .A(A),\r
- .B(B),\r
- .Y(Y)\r
- );\r
- endgenerate\r
-endmodule\r
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ * 2019 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * ---
+ *
+ * Tech-mapping rules for decomposing arbitrarily-sized $mul cells
+ * into an equivalent collection of smaller `DSP_NAME cells (with the
+ * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
+ * to $shl and $add cells.
+ *
+ */
+
+`ifndef DSP_A_MAXWIDTH
+$fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
+`endif
+`ifndef DSP_B_MAXWIDTH
+$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
+`endif
+`ifndef DSP_B_MAXWIDTH
+$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
+`endif
+`ifndef DSP_A_MAXWIDTH_PARTIAL
+`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
+`endif
+`ifndef DSP_B_MAXWIDTH_PARTIAL
+`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
+`endif
+
+`ifndef DSP_NAME
+$fatal(1, "Macro DSP_NAME must be defined");
+`endif
+
+`define MAX(a,b) (a > b ? a : b)
+`define MIN(a,b) (a < b ? a : b)
+
+(* techmap_celltype = "$mul $__mul" *)
+module _80_mul (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ parameter _TECHMAP_CELLTYPE_ = "";
+
+ generate
+ if (0) begin end
+`ifdef DSP_A_MINWIDTH
+ else if (A_WIDTH < `DSP_A_MINWIDTH)
+ wire _TECHMAP_FAIL_ = 1;
+`endif
+`ifdef DSP_B_MINWIDTH
+ else if (B_WIDTH < `DSP_B_MINWIDTH)
+ wire _TECHMAP_FAIL_ = 1;
+`endif
+`ifdef DSP_Y_MINWIDTH
+ else if (Y_WIDTH < `DSP_Y_MINWIDTH)
+ wire _TECHMAP_FAIL_ = 1;
+`endif
+`ifdef DSP_SIGNEDONLY
+ else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
+ \$mul #(
+ .A_SIGNED(1),
+ .B_SIGNED(1),
+ .A_WIDTH(A_WIDTH + 1),
+ .B_WIDTH(B_WIDTH + 1),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A({1'b0, A}),
+ .B({1'b0, B}),
+ .Y(Y)
+ );
+`endif
+ else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
+ \$mul #(
+ .A_SIGNED(B_SIGNED),
+ .B_SIGNED(A_SIGNED),
+ .A_WIDTH(B_WIDTH),
+ .B_WIDTH(A_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A(B),
+ .B(A),
+ .Y(Y)
+ );
+ else begin
+ wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+`ifdef DSP_SIGNEDONLY
+ localparam sign_headroom = 1;
+`else
+ localparam sign_headroom = 0;
+`endif
+
+ genvar i;
+ if (A_WIDTH > `DSP_A_MAXWIDTH) begin
+ localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
+ localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
+ localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
+ localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
+ if (A_SIGNED && B_SIGNED) begin : blk
+ (* force_downto *)
+ wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
+ wire signed [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
+ wire signed [Y_WIDTH-1:0] partial_sum [n:0];
+ end
+ else begin : blk
+ (* force_downto *)
+ wire [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
+ wire [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] partial_sum [n:0];
+ end
+
+ for (i = 0; i < n; i=i+1) begin:sliceA
+ \$__mul #(
+ .A_SIGNED(sign_headroom),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(partial_Y_WIDTH)
+ ) mul (
+ .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
+ .B(B),
+ .Y(blk.partial[i])
+ );
+ // TODO: Currently a 'cascade' approach to summing the partial
+ // products is taken here, but a more efficient 'binary
+ // reduction' approach also exists...
+ if (i == 0)
+ assign blk.partial_sum[i] = blk.partial[i];
+ else
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
+ end
+
+ \$__mul #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(last_A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(last_Y_WIDTH)
+ ) sliceA.last (
+ .A(A[A_WIDTH-1 -: last_A_WIDTH]),
+ .B(B),
+ .Y(blk.last_partial)
+ );
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
+ end
+ else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
+ localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
+ localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
+ localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
+ localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
+ if (A_SIGNED && B_SIGNED) begin : blk
+ (* force_downto *)
+ wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
+ wire signed [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
+ wire signed [Y_WIDTH-1:0] partial_sum [n:0];
+ end
+ else begin : blk
+ (* force_downto *)
+ wire [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
+ wire [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] partial_sum [n:0];
+ end
+
+ for (i = 0; i < n; i=i+1) begin:sliceB
+ \$__mul #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(sign_headroom),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
+ .Y_WIDTH(partial_Y_WIDTH)
+ ) mul (
+ .A(A),
+ .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
+ .Y(blk.partial[i])
+ );
+ // TODO: Currently a 'cascade' approach to summing the partial
+ // products is taken here, but a more efficient 'binary
+ // reduction' approach also exists...
+ if (i == 0)
+ assign blk.partial_sum[i] = blk.partial[i];
+ else
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
+ end
+
+ \$__mul #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(last_B_WIDTH),
+ .Y_WIDTH(last_Y_WIDTH)
+ ) mul_sliceB_last (
+ .A(A),
+ .B(B[B_WIDTH-1 -: last_B_WIDTH]),
+ .Y(blk.last_partial)
+ );
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
+ end
+ else begin
+ if (A_SIGNED) begin : blkA
+ wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
+ end
+ else begin : blkA
+ wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
+ end
+ if (B_SIGNED) begin : blkB
+ wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
+ end
+ else begin : blkB
+ wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
+ end
+
+ `DSP_NAME #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(`DSP_A_MAXWIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH),
+ .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
+ ) _TECHMAP_REPLACE_ (
+ .A(blkA.Aext),
+ .B(blkB.Bext),
+ .Y(Y)
+ );
+ end
+ end
+ endgenerate
+endmodule
+
+(* techmap_celltype = "$mul $__mul" *)
+module _90_soft_mul (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ // Indirection necessary since mapping
+ // back to $mul will cause recursion
+ generate
+ if (A_SIGNED && !B_SIGNED)
+ \$__soft_mul #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(1),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH+1),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .B({1'b0,B}),
+ .Y(Y)
+ );
+ else if (!A_SIGNED && B_SIGNED)
+ \$__soft_mul #(
+ .A_SIGNED(1),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH+1),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A({1'b0,A}),
+ .B(B),
+ .Y(Y)
+ );
+ else
+ \$__soft_mul #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .B(B),
+ .Y(Y)
+ );
+ endgenerate
+endmodule
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