static void
blorp_emit_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface,
+ enum isl_aux_op op,
void *state, uint32_t state_offset,
const bool color_write_disables[4],
bool is_render_target)
isl_dev->ss.clear_color_state_offset,
surface->clear_color_addr, *clear_addr);
#elif GEN_GEN >= 7
- struct blorp_address dst_addr = blorp_get_surface_base_address(batch);
- dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
- blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,
- isl_dev->ss.clear_value_size);
+ if (op == ISL_AUX_OP_FULL_RESOLVE || op == ISL_AUX_OP_PARTIAL_RESOLVE) {
+ struct blorp_address dst_addr = blorp_get_surface_base_address(batch);
+ dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
+ blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,
+ isl_dev->ss.clear_value_size);
+ }
#else
unreachable("Fast clears are only supported on gen7+");
#endif
if (params->dst.enabled) {
blorp_emit_surface_state(batch, ¶ms->dst,
+ params->fast_clear_op,
surface_maps[BLORP_RENDERBUFFER_BT_INDEX],
surface_offsets[BLORP_RENDERBUFFER_BT_INDEX],
params->color_write_disable, true);
if (params->src.enabled) {
blorp_emit_surface_state(batch, ¶ms->src,
+ params->fast_clear_op,
surface_maps[BLORP_TEXTURE_BT_INDEX],
surface_offsets[BLORP_TEXTURE_BT_INDEX],
NULL, false);