wishbone: decoder: fix slave cyc generation in registered mode

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index bca7fce4850cd50e78c186cb125ab80420cb0b0b..b464adea8dfe6e3ad1f3c90ac4bb45bb5e985e88 100644 (file)
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -113,7 +113,7 @@ class Decoder:
                # combine cyc with slave selection signals
                i = 0
                for slave in self.slaves:
-                       comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i]))
+                       comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i]))
                        i += 1
                
                # generate master ack (resp. err) by ORing all slave acks (resp. errs)