targets: always use sys_clk_freq on SDRAM modules.

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index d6d059f75d350d4a13b08308b54568a5b8487624..e3ca8683793948e9c062b9dfe66e97eca2a6f1c3 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
-                module                  = IS42S16160(self.clk_freq, "1:1"),
+                module                  = IS42S16160(sys_clk_freq, "1:1"),
                 origin                  = self.mem_map["main_ram"],
                 size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 6160dc9fef6b9f37ba52f1935d12db6cb76f9f9b..a15c9bab964e24f940fda915840539d672955ea4 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -61,7 +61,7 @@ class BaseSoC(SoCCore):
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
-                module                  = MT41J256M16(self.clk_freq, "1:4"),
+                module                  = MT41J256M16(sys_clk_freq, "1:4"),
                 origin                  = self.mem_map["main_ram"],
                 size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),