cpu/vexriscv: bump submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 747a2e012f43d13c3487acc3c758477aad277559..854f9bd2282c97251ce65e4117c5cf1630722004 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 747a2e012f43d13c3487acc3c758477aad277559
+Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004