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winsys/amdgpu: fix ADDR_REGISTER_VALUE::backendDisables
author
Marek Olšák
<marek.olsak@amd.com>
Thu, 26 Jan 2017 01:16:18 +0000
(
02:16
+0100)
committer
Marek Olšák
<marek.olsak@amd.com>
Mon, 30 Jan 2017 12:27:14 +0000
(13:27 +0100)
This would be a fix if the value was used anywhere.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
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diff --git
a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 08989b5cf531106a6cdac0a2761b341aaaa2826b..abe2b2a67af2dfe1eb970f81f299ca82348587d0 100644
(file)
--- a/
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@
-111,7
+111,7
@@
ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
- regValue.backendDisables = ws->amdinfo.
backend_disable[0]
;
+ regValue.backendDisables = ws->amdinfo.
enabled_rb_pipes_mask
;
regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
if (ws->info.chip_class == SI) {