clarify intro

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 1255e4d5249dc1a2f24a1e100a93f4e7b120b95b..869f50c0944b3810bb3a3db6ad8a7c34adefbf11 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -190,14 +190,15 @@ AVX-512 and SVE2 truly "Scalable".*
 
 # Major opcodes summary
 
-Simple-V itself only requires four instructions with 6-bit Minor XO
+Simple-V itself only requires five instructions with 6-bit Minor XO
 (bits 26-31), and the SVP64 Prefix Encoding requires
 25% space of the EXT001 Major Opcode.
 There are **no** Vector Instructions and consequently **no further
 opcode space is required**.
 
 That said: for the target workloads for which Scalable Vectors are typically
-used, the Scalar ISA on which SV critically relies is somewhat anaemic.
+used, the Scalar ISA on which those workloads critically rely
+is somewhat anaemic.
 The Libre-SOC Team has therefore been addressing that by developing
 a number of Scalar instructions in specialist areas (Big Integer,
 Cryptography, 3D, Audio/Video, DSP) and it is these which require
@@ -245,10 +246,12 @@ is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
 a Hybrid 3D CPU-VPU-GPU.
 
-**Whilst SVP64 is only 4 instructions
+**Whilst SVP64 is only 5 instructions
 the heavy focus on VSX for the past 12 years has left the SFFS Level
-anaemic and out-of-date compared to ARM and x86. Approximately
-100 additional Scalar Instructions are up for proposal**
+anaemic and out-of-date compared to ARM and x86. This is partially
+a blessing as the Scalar ISA has remained clean. Approximately
+100 additional (optional) Scalar Instructions are up for proposal to bring SFFS
+up-to-date**
 
 # Other