Only generate VMOV.I64 instructions for loading constant floating point values if...

	PR target/2006764
	* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
	instruction if supported by the currently selected fpu variant.
	* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
	* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 03f331955c7cc2caf13d192857e6a90937c9b874..39814fcd4d0d44c5c7f813af4655d4bb14830ee1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
+2016-05-25  Chua Zheng Leong  <chuazl@comp.nus.edu.sg>
+
+       PR target/2006764
+       * config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
+       instruction if supported by the currently selected fpu variant.
+       * testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
+       * testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
+
 2016-05-24  Maciej W. Rozycki  <macro@imgtec.com>
-    
+
        * config/tc-mips.c (mips_fix_adjustable): Also return 0 for
        jump relocations against MIPS16 or microMIPS symbols on RELA
        targets.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 50a658b8c158bfad6965af857ff1f430d1ee1a74..fe46cc438989ad14f876c94be5b4ac22e3716584 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8000,7 +8000,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
                  return TRUE;
                }
            }
-         else if (t == CONST_VEC)
+         else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
            {
              int op = 0;
              unsigned immbits = 0;

diff --git a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
index e443530414b4f8564fb7b4980463e53c8e719042..b5ad34d27521abc68567330594b01a20473852b3 100644 (file)
--- a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
+++ b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
@@ -32,4 +32,5 @@ Disassembly of section \.text:
 0[0-9a-fx]+ .*(00000000|40400000)      .*
 0[0-9a-fx]+ .*(40400000|00000000)      .*
 0[0-9a-fx]+ .*42000000         .*
+0[0-9a-fx]+ .*ed1fbb01         vldr    d11, \[pc, #-4\].*
 #pass

diff --git a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.s b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.s
index 172b57d62d593bb4418db449a1ef466daa2432f2..542206f38ad6af437ad8d65beaa4fb74c13176be 100644 (file)
--- a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.s
+++ b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.s
@@ -42,5 +42,7 @@
   vldr s0,=0x42000000
   .pool
 
-  nop
+  # PR 20067
+  FLDD D11, =0
+  .pool