[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo

opcode/
	PR target/20666
	* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.

gas/
	* testsuite/gas/aarch64/alias-2.d: Update expected results.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4ecacf4275787b001f7b9683b153f67a05f87f86..ca6667233e0b920614c6251bb926b8519ec0e85e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2016-10-11  Jiong Wang  <jiong.wang@arm.com>
+
+       PR target/20666
+       * testsuite/gas/aarch64/alias-2.d: Update expected results.
+
 2016-10-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.

diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d
index 64a94a4bc56462c62da9129fb0ca11d2eb0f8820..45ddcf5905a677ab807c9e8f7d93dd8b10bd77a1 100644 (file)
--- a/gas/testsuite/gas/aarch64/alias-2.d
+++ b/gas/testsuite/gas/aarch64/alias-2.d
@@ -3,9 +3,9 @@
 
 .*:     file format .*
 
-Disassembly of section \.text:
+Disassembly of section .*:
 
-0000000000000000 <.*>:
+.* <.*>:
    [0-9a-f]+:  b34107e0        bfxil   x0, xzr, #1, #1
    [0-9a-f]+:  b3410420        bfxil   x0, x1, #1, #1
    [0-9a-f]+:  b341043f        bfxil   xzr, x1, #1, #1
@@ -78,23 +78,23 @@ Disassembly of section \.text:
  [0-9a-f]+:    b3613820        bfi     x0, x1, #31, #15
  [0-9a-f]+:    b361383f        bfi     xzr, x1, #31, #15
  [0-9a-f]+:    b3613bff        bfc     xzr, #31, #15
- [0-9a-f]+:    b34003e0        bfxil   x0, xzr, #0, #1
+ [0-9a-f]+:    b37f03e0        bfc     x0, #1, #1
+ [0-9a-f]+:    b37f03ff        bfc     xzr, #1, #1
+ [0-9a-f]+:    b37f1fe0        bfc     x0, #1, #8
+ [0-9a-f]+:    b37f1fff        bfc     xzr, #1, #8
+ [0-9a-f]+:    b37f3be0        bfc     x0, #1, #15
+ [0-9a-f]+:    b37f3bff        bfc     xzr, #1, #15
+ [0-9a-f]+:    b37003e0        bfc     x0, #16, #1
+ [0-9a-f]+:    b37003ff        bfc     xzr, #16, #1
+ [0-9a-f]+:    b3701fe0        bfc     x0, #16, #8
+ [0-9a-f]+:    b3701fff        bfc     xzr, #16, #8
+ [0-9a-f]+:    b3703be0        bfc     x0, #16, #15
+ [0-9a-f]+:    b3703bff        bfc     xzr, #16, #15
+ [0-9a-f]+:    b36103e0        bfc     x0, #31, #1
  [0-9a-f]+:    b36103ff        bfc     xzr, #31, #1
- [0-9a-f]+:    b3401fe0        bfxil   x0, xzr, #0, #8
- [0-9a-f]+:    b3611fff        bfc     xzr, #31, #8
- [0-9a-f]+:    b3403be0        bfxil   x0, xzr, #0, #15
- [0-9a-f]+:    b3613bff        bfc     xzr, #31, #15
- [0-9a-f]+:    b34003e0        bfxil   x0, xzr, #0, #1
- [0-9a-f]+:    b36103ff        bfc     xzr, #31, #1
- [0-9a-f]+:    b3401fe0        bfxil   x0, xzr, #0, #8
- [0-9a-f]+:    b3611fff        bfc     xzr, #31, #8
- [0-9a-f]+:    b3403be0        bfxil   x0, xzr, #0, #15
- [0-9a-f]+:    b3613bff        bfc     xzr, #31, #15
- [0-9a-f]+:    b34003e0        bfxil   x0, xzr, #0, #1
- [0-9a-f]+:    b36103ff        bfc     xzr, #31, #1
- [0-9a-f]+:    b3401fe0        bfxil   x0, xzr, #0, #8
+ [0-9a-f]+:    b3611fe0        bfc     x0, #31, #8
  [0-9a-f]+:    b3611fff        bfc     xzr, #31, #8
- [0-9a-f]+:    b3403be0        bfxil   x0, xzr, #0, #15
+ [0-9a-f]+:    b3613be0        bfc     x0, #31, #15
  [0-9a-f]+:    b3613bff        bfc     xzr, #31, #15
  [0-9a-f]+:    dac00fe0        rev     x0, xzr
  [0-9a-f]+:    dac00c20        rev     x0, x1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 65cf0d7591e2c362e0bbf0a611bc1a5177c69a5c..3ac9c3fba79f3b03870d0a0c89ecadc88da4c372 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-10-11  Jiong Wang  <jiong.wang@arm.com>
+
+       PR target/20666
+       * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
+
 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 
        PR target/20667

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index dd2859b42362b8b85428e7891047bbf6dc72ee6a..34be79482a60dbae687355d83eb67b24dddd837d 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1539,7 +1539,7 @@ convert_bfc_to_bfm (aarch64_inst *inst)
   /* Insert XZR.  */
   copy_operand_info (inst, 3, 2);
   copy_operand_info (inst, 2, 1);
-  copy_operand_info (inst, 2, 0);
+  copy_operand_info (inst, 0, 0);
   inst->operands[1].reg.regno = 0x1f;
 
   /* Convert the immedate operand.  */