Get basic full-system working with AtomicSimpleCPU.

SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb

diff --git a/SConscript b/SConscript
index a2d5de2795b59dcc6786793aa05f5f707700c2a4..4cc232bfdfaf4e6cefedfb2d36666f844fb95f6c 100644 (file)
--- a/SConscript
+++ b/SConscript
@@ -207,7 +207,6 @@ full_system_sources = Split('''
        dev/platform.cc
         dev/simconsole.cc
        dev/simple_disk.cc
-       dev/sinic.cc
        dev/tsunami.cc
        dev/tsunami_cchip.cc
        dev/tsunami_io.cc
@@ -228,6 +227,7 @@ full_system_sources = Split('''
 
        sim/pseudo_inst.cc
         ''')
+#      dev/sinic.cc
 
 
 if env['TARGET_ISA'] == 'alpha':

diff --git a/configs/test/SysPaths.py b/configs/test/SysPaths.py
index 7f231916c355a5e6726cd9accb2ef538fdf3f37e..c7c7db4e7f01376ac800ca49c3045936a9a7fa83 100644 (file)
--- a/configs/test/SysPaths.py
+++ b/configs/test/SysPaths.py
@@ -22,11 +22,11 @@ BINDIR = SYSTEMDIR + '/binaries'
 DISKDIR = SYSTEMDIR + '/disks'
 
 def disk(file):
-    return '%s/%s' % (DISKDIR, file)
+    return os.path.join(DISKDIR, file)
 
 def binary(file):
-    return '%s/%s' % (BINDIR, file)
+    return os.path.join(BINDIR, file)
 
 def script(file):
-    return '%s/%s' % ('/z/saidi/work/m5.newmem/configs/boot', file)
+    return os.path.join(SYSTEMDIR, 'boot', file)
 

diff --git a/configs/test/fs.py b/configs/test/fs.py
index ce121bd76fb97d6dafa9babb411eaf40f4c2a3a9..fdbf86abef1f69c6a4820bd1bd9a5404fba9a0c3 100644 (file)
--- a/configs/test/fs.py
+++ b/configs/test/fs.py
@@ -181,9 +181,9 @@ class LinuxAlphaSystem(LinuxAlphaSystem):
                              read_only=True)
     simple_disk = SimpleDisk(disk=Parent.raw_image)
     intrctrl = IntrControl()
-    cpu = SimpleCPU(mem=Parent.magicbus2)
+    cpu = AtomicSimpleCPU(mem=Parent.magicbus2)
     sim_console = SimConsole(listener=ConsoleListener(port=3456))
-    kernel = '/z/saidi/work/m5.newmem/build/vmlinux'
+    kernel = binary('vmlinux')
     pal = binary('ts_osfpal')
     console = binary('console')
     boot_osflags = 'root=/dev/hda1 console=ttyS0'

diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc
index 8c38fe0d4617db89c7acbd40e14df5bb787c1b60..35a69cd4a7fe739350677518d2c79bacff5c5b04 100644 (file)
--- a/cpu/simple/atomic.cc
+++ b/cpu/simple/atomic.cc
@@ -100,6 +100,9 @@ AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
 void
 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
 {
+    if (status == RangeChange)
+        return;
+
     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 }
 
@@ -227,10 +230,13 @@ AtomicSimpleCPU::suspendContext(int thread_num)
     assert(cpuXC);
 
     assert(_status == Running);
-    assert(tickEvent.scheduled());
+
+    // tick event may not be scheduled if this gets called from inside
+    // an instruction's execution, e.g. "quiesce"
+    if (tickEvent.scheduled())
+        tickEvent.deschedule();
 
     notIdleFraction--;
-    tickEvent.deschedule();
     _status = Idle;
 }
 
@@ -417,6 +423,8 @@ AtomicSimpleCPU::tick()
     for (int i = 0; i < width; ++i) {
         numCycles++;
 
+        checkForInterrupts();
+
         ifetch_req->resetMin();
         ifetch_pkt->reset();
         Fault fault = setupFetchPacket(ifetch_pkt);
@@ -452,7 +460,8 @@ AtomicSimpleCPU::tick()
         advancePC(fault);
     }
 
-    tickEvent.schedule(curTick + latency);
+    if (_status != Idle)
+        tickEvent.schedule(curTick + latency);
 }
 
 

diff --git a/cpu/simple/base.cc b/cpu/simple/base.cc
index 40868e74d7b7e0b9a95acf2228f32982cacb1eda..30c002ed5062c394d487c3bd79767d37b96b8a87 100644 (file)
--- a/cpu/simple/base.cc
+++ b/cpu/simple/base.cc
@@ -307,8 +307,7 @@ void
 BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
-    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
-        status() != IcacheAccessComplete) {
+    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
         int ipl = 0;
         int summary = 0;
         checkInterrupts = false;

diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index 891c462b57102d68be499037c9e3aa77f0802032..2d04ecd098ae09b2d3ae0115f0a2fa2618a38904 100644 (file)
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -259,12 +259,6 @@ class IdeDisk : public SimObject
      */
     void reset(int id);
 
-    /**
-     * Register statistics.
-     */
-    void regStats();
-
-
     /**
      * Set the controller for this device
      * @param c The IDE controller

diff --git a/dev/io_device.cc b/dev/io_device.cc
index 24f33d84d8b1c3f42dbd2483e22a9a4389c74197..aa411d1327a4a16587ea254c64efeda615e25688 100644 (file)
--- a/dev/io_device.cc
+++ b/dev/io_device.cc
@@ -160,8 +160,7 @@ DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event,
     basePkt.flags = 0;
     basePkt.coherence = NULL;
     basePkt.senderState = NULL;
-    basePkt.src = 0;
-    basePkt.dest = 0;
+    basePkt.dest = Packet::Broadcast;
     basePkt.cmd = cmd;
     basePkt.result = Unknown;
     basePkt.req = NULL;

diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index dfb1d48f6d7446576584e6790f09e283d01bff3a..a8c742b07629f2d8dab4e2b3be83086f5f008081 100644 (file)
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -165,6 +165,7 @@ PciConfigAll::write(Packet &pkt)
       default:
         panic("invalid pci config write size\n");
     }
+    pkt.result = Success;
     return pioDelay;
 }
 

diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index f51516098dd965bbc1d80ddb5c92012f9baf4200..205a93c760a2fdbb74806b38903f5e67f517530b 100644 (file)
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -3,6 +3,7 @@ from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
 from ExeTrace import ExecutionTrace
+from Debug import Debug
 
 class Root(SimObject):
     type = 'Root'
@@ -19,3 +20,4 @@ class Root(SimObject):
     trace = Trace()
     exetrace = ExecutionTrace()
     serialize = Serialize()
+    debug = Debug()