interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 905ef58675613062bebee6547c183d7243c3e7a8..534a0cca2a318e70e382f9cb7b4bbb30ea2274da 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -56,7 +56,7 @@ def r_description(data_width, id_width):
     ]
 
 class AXIInterface(Record):
-    def __init__(self, data_width, address_width, mode="master", id_width=1, clock_domain="sys"):
+    def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.id_width      = id_width