Add support for the LMBD (left-most bit detect) instruction to the PRU assembler.

include	* opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas 	* testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
 	* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3c3ce6e6a7bdd05ac217c98ce6b1083fcda1ff79..d0ed87a345b81e0c2d2113d55b44d0e57f4d5b62 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
+
+       * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit
+       detect).
+       * testsuite/gas/pru/misc.d: Update expected disassembly.
+
 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * config/tc-aarch64.c: Fix comment.

diff --git a/gas/testsuite/gas/pru/misc.d b/gas/testsuite/gas/pru/misc.d
index 7c791e63f4f30aab951801fbe7e089de421c49ca..ac778db545be8123a1af791b3afe92615673d69e 100644 (file)
--- a/gas/testsuite/gas/pru/misc.d
+++ b/gas/testsuite/gas/pru/misc.d
@@ -9,3 +9,6 @@ Disassembly of section .text:
 0+0000 <[^>]*> 2a000000        halt
 0+0004 <[^>]*> 3e800000        slp     1
 0+0008 <[^>]*> 3e000000        slp     0
+0+000c <[^>]*> 2701e1e0        lmbd    r0, r1, 1
+0+0010 <[^>]*> 2700e100        lmbd    r0.b0, r1, 0
+0+0014 <[^>]*> 2642e1e0        lmbd    r0, r1, sp.b2

diff --git a/gas/testsuite/gas/pru/misc.s b/gas/testsuite/gas/pru/misc.s
index cfe4d88fcead1cc6a522ad9d2fff9b41924ad0ce..42e08a75799a7a252a1c91e013fd7a15809c5647 100644 (file)
--- a/gas/testsuite/gas/pru/misc.s
+++ b/gas/testsuite/gas/pru/misc.s
@@ -4,3 +4,6 @@ foo:
        halt
        slp     1
        slp     0
+       lmbd r0, r1, 0x1
+       lmbd r0.b0, r1, 0x0
+       lmbd r0, r1, r2.b2

diff --git a/gas/write.c b/gas/write.c
index 054f27987d51f1732afdc81bbc9e19a95160c53f..36fc40488d97f6c986958b502bb6c44dbed8f691 100644 (file)
--- a/gas/write.c
+++ b/gas/write.c
@@ -771,6 +771,22 @@ resolve_reloc_expr_symbols (void)
     }
 }
 
+static bfd_boolean
+is_dwo_section (asection *sec)
+{
+  const char *name;
+  int len;
+
+  if (sec == NULL || (name = bfd_section_name (sec)) == NULL)
+    return FALSE;
+
+  len = strlen (name);
+  if (len < 5)
+    return FALSE;
+
+  return strncmp (name + len - 4, ".dwo", 4) == 0;
+}
+
 /* This pass over fixups decides whether symbols can be replaced with
    section symbols.  */
 
@@ -899,6 +915,14 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 #endif
       }
 
+  /* PR 26841: DWO sections are not supposed to have relocations.  */
+  if (is_dwo_section (sec) && seginfo->fix_root != NULL)
+    {
+      as_bad (_("DWO section '%s' contains unresolved expressions - this is not allowed"),
+             bfd_section_name (sec));
+      seginfo->fix_root = NULL; /* FIXME: Memory leak ?  */
+    }
+
   dump_section_relocs (abfd, sec, stderr);
 }
 

diff --git a/include/ChangeLog b/include/ChangeLog
index 5a4f453d2aab511aabecd6c3c8ea403e5d05085c..f54d85d5b697b40f092d5aeaa2438c969c9112c2 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
+
+       * opcode/pru.h: Add LMBD (left-most bit detect) opcode index.
+
 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * opcode/aarch64.h (enum aarch64_opnd): Add new operand AARCH64_OPND_Rt_LS64.

diff --git a/include/opcode/pru.h b/include/opcode/pru.h
index 74cc27a544f373ad5a3975adc47f7c5fe0854ab4..76988311902dc523e8acb4eaa9ec9758293b0699 100644 (file)
--- a/include/opcode/pru.h
+++ b/include/opcode/pru.h
@@ -44,25 +44,27 @@ enum overflow_type
   no_overflow
 };
 
-enum opcode_format_type {
-    opcode_format1,
-    opcode_format2ab,
-    opcode_format2abl,
-    opcode_format2c,
-    opcode_format2de,
-    opcode_format45,
-    opcode_format6
+enum opcode_format_type
+{
+  opcode_format1,
+  opcode_format2ab,
+  opcode_format2abl,
+  opcode_format2c,
+  opcode_format2de,
+  opcode_format45,
+  opcode_format6
 };
 
 /* Opcode ID listing. Used for indexing by the simulator.  */
-enum pru_instr_type {
-    prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb,
-    prui_rsc, prui_and, prui_or,  prui_xor, prui_min, prui_max, prui_clr,
-    prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_halt, prui_slp,
-    prui_xin, prui_xout, prui_xchg, prui_sxin, prui_sxout, prui_sxchg,
-    prui_loop, prui_iloop, prui_qbgt, prui_qbge, prui_qblt, prui_qble,
-    prui_qbeq, prui_qbne, prui_qba, prui_qbbs, prui_qbbc, prui_lbbo,
-    prui_sbbo, prui_lbco, prui_sbco
+enum pru_instr_type
+{
+  prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb,
+  prui_rsc, prui_and, prui_or,  prui_xor, prui_min, prui_max, prui_clr,
+  prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_lmbd,
+  prui_halt, prui_slp, prui_xin, prui_xout, prui_xchg, prui_sxin,
+  prui_sxout, prui_sxchg, prui_loop, prui_iloop, prui_qbgt, prui_qbge,
+  prui_qblt, prui_qble, prui_qbeq, prui_qbne, prui_qba, prui_qbbs,
+  prui_qbbc, prui_lbbo, prui_sbbo, prui_lbco, prui_sbco
 };
 
 /* This structure holds information for a particular instruction.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 34b2b62d51facbc6a8efbfc36fd04d0fb342711b..3b7354c5f21e37382608354092544d05c2d8a83c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
+
+       * pru-opc.c: Add opcode description for LMBD (left-most bit
+       detect).
+
 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * aarch64-opc.c: Add ACCDATA_EL1 system register

diff --git a/opcodes/pru-opc.c b/opcodes/pru-opc.c
index f1fb7fefe1e093f3fb4e3731ec424d6ecc0c27a7..05ddfb0358bc3a4dd8b542fb18ad16c2db1eaa46 100644 (file)
--- a/opcodes/pru-opc.c
+++ b/opcodes/pru-opc.c
@@ -121,6 +121,8 @@ const struct pru_opcode pru_opcodes[] =
    OP_MATCH_JAL, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
   { "ldi", prui_ldi, "d,W",
    OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
+  { "lmbd", prui_lmbd, "d,s,b",
+   OP_MATCH_LMBD, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed8_overflow},
   { "halt", prui_halt, "",
    OP_MATCH_HALT, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow},
   { "slp", prui_slp, "w",