back.rtlil: fix guard for division by zero.

Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 3838101384f3f175db0c696b1860fc8136721863..f7727782968ef8e51e0651c798af03ed94d5f249 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -558,7 +558,7 @@ class _RHSValueCompiler(_ValueCompiler):
             self.s.rtlil.cell("$mux", ports={
                 "\\A": divmod_res,
                 "\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))),
-                "\\S": self(lhs == 0),
+                "\\S": self(rhs == 0),
                 "\\Y": res,
             }, params={
                 "WIDTH": res_bits