back.rtlil: fix guard for division by zero.
authorwhitequark <whitequark@whitequark.org>
Wed, 15 Jul 2020 04:09:58 +0000 (04:09 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 14:53:34 +0000 (14:53 +0000)
Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.

nmigen/back/rtlil.py

index 3838101384f3f175db0c696b1860fc8136721863..f7727782968ef8e51e0651c798af03ed94d5f249 100644 (file)
@@ -558,7 +558,7 @@ class _RHSValueCompiler(_ValueCompiler):
             self.s.rtlil.cell("$mux", ports={
                 "\\A": divmod_res,
                 "\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))),
-                "\\S": self(lhs == 0),
+                "\\S": self(rhs == 0),
                 "\\Y": res,
             }, params={
                 "WIDTH": res_bits