ARM: Move the templates for predicated instructions into a separate file.

This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa

diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 03eb3a492ff30c8e0a03826e23f082a61705e184..d5e3fec1978cbd9b2145f283b6bf0132daedec04 100644 (file)
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -40,58 +40,6 @@
 //
 // Authors: Stephen Hines
 
-////////////////////////////////////////////////////////////////////
-//
-// Predicated Instruction Execution
-//
-
-let {{
-    predicateTest = 'testPredicate(CondCodes, condCode)'
-}};
-
-def template PredOpExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-    {
-        Fault fault = NoFault;
-        uint64_t resTemp = 0;
-        resTemp = resTemp;
-        %(op_decl)s;
-        %(op_rd)s;
-
-        if (%(predicate_test)s)
-        {
-            %(code)s;
-            if (fault == NoFault)
-            {
-                %(op_wb)s;
-            }
-        }
-
-        return fault;
-    }
-}};
-
-def template DataDecode {{
-    if (machInst.opcode4 == 0) {
-        if (machInst.sField == 0)
-            return new %(class_name)sImm(machInst);
-        else
-            return new %(class_name)sImmCc(machInst);
-    } else {
-        if (machInst.sField == 0)
-            return new %(class_name)s(machInst);
-        else
-            return new %(class_name)sCc(machInst);
-    }
-}};
-
-def template DataImmDecode {{
-    if (machInst.sField == 0)
-        return new %(class_name)s(machInst);
-    else
-        return new %(class_name)sCc(machInst);
-}};
-
 let {{
  
      calcCcCode = '''

diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index a7aa0b2ed9b65cea4108673b8f288fa6465ae68b..1bd70e54b34b8df952f6c212d4c6be07fa9f2fa6 100644 (file)
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -52,8 +52,6 @@ let {{
         else:
             eaCode += '0;'
 
-        predicateTest = 'testPredicate(CondCodes, condCode)'
-
         iop = InstObjParams(name, Name, base,
                             {'ea_code': eaCode,
                              'memacc_code': accCode,

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
new file mode 100644 (file)
index 0000000..c7f79aa
--- /dev/null
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -0,0 +1,93 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2007-2008 The Florida State University
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Stephen Hines
+
+////////////////////////////////////////////////////////////////////
+//
+// Predicated Instruction Execution
+//
+
+let {{
+    predicateTest = 'testPredicate(CondCodes, condCode)'
+}};
+
+def template PredOpExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+        uint64_t resTemp = 0;
+        resTemp = resTemp;
+        %(op_decl)s;
+        %(op_rd)s;
+
+        if (%(predicate_test)s)
+        {
+            %(code)s;
+            if (fault == NoFault)
+            {
+                %(op_wb)s;
+            }
+        }
+
+        return fault;
+    }
+}};
+
+def template DataDecode {{
+    if (machInst.opcode4 == 0) {
+        if (machInst.sField == 0)
+            return new %(class_name)sImm(machInst);
+        else
+            return new %(class_name)sImmCc(machInst);
+    } else {
+        if (machInst.sField == 0)
+            return new %(class_name)s(machInst);
+        else
+            return new %(class_name)sCc(machInst);
+    }
+}};
+
+def template DataImmDecode {{
+    if (machInst.sField == 0)
+        return new %(class_name)s(machInst);
+    else
+        return new %(class_name)sCc(machInst);
+}};

diff --git a/src/arch/arm/isa/templates/templates.isa b/src/arch/arm/isa/templates/templates.isa
index 65175d3cf187b9ca270fe6071a53dddd85b7c808..f10e8a07be6ada2d5f7f8ae3fcf2373ba9d92b70 100644 (file)
--- a/src/arch/arm/isa/templates/templates.isa
+++ b/src/arch/arm/isa/templates/templates.isa
@@ -37,5 +37,8 @@
 //
 // Authors: Gabe Black
 
+//Templates for predicated instructions
+##include "pred.isa"
+
 //Templates for memory instructions
 ##include "mem.isa"