boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:41:53
-gem5 started May 7 2014 10:52:34
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:31
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1885187323500 because m5_exit instruction encountered
+Exiting @ tick 1883224346500 because m5_exit instruction encountered
sim_ticks 1883224346500 # Number of ticks simulated
final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 293967 # Simulator instruction rate (inst/s)
-host_op_rate 293967 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9864607727 # Simulator tick rate (ticks/s)
-host_mem_usage 317632 # Number of bytes of host memory used
-host_seconds 190.91 # Real time elapsed on the host
+host_inst_rate 279379 # Simulator instruction rate (inst/s)
+host_op_rate 279379 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9375076807 # Simulator tick rate (ticks/s)
+host_mem_usage 311380 # Number of bytes of host memory used
+host_seconds 200.88 # Real time elapsed on the host
sim_insts 56120453 # Number of instructions simulated
sim_ops 56120453 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: Obsolete M5 ivlb instruction encountered.
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 13:05:58
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:21:02
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 121062000
-Exiting @ tick 1906207240000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 119596000
+Exiting @ tick 1905067807000 because m5_exit instruction encountered
sim_ticks 1905067807000 # Number of ticks simulated
final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 133407 # Simulator instruction rate (inst/s)
-host_op_rate 133407 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4441980470 # Simulator tick rate (ticks/s)
-host_mem_usage 322876 # Number of bytes of host memory used
-host_seconds 428.88 # Real time elapsed on the host
+host_inst_rate 163944 # Simulator instruction rate (inst/s)
+host_op_rate 163944 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5458738398 # Simulator tick rate (ticks/s)
+host_mem_usage 318552 # Number of bytes of host memory used
+host_seconds 348.99 # Real time elapsed on the host
sim_insts 57215334 # Number of instructions simulated
sim_ops 57215334 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 13:05:52
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:51
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1860172195000 because m5_exit instruction encountered
+Exiting @ tick 1859038679000 because m5_exit instruction encountered
sim_ticks 1859038679000 # Number of ticks simulated
final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 145866 # Simulator instruction rate (inst/s)
-host_op_rate 145866 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5123409698 # Simulator tick rate (ticks/s)
-host_mem_usage 320704 # Number of bytes of host memory used
-host_seconds 362.85 # Real time elapsed on the host
+host_inst_rate 164458 # Simulator instruction rate (inst/s)
+host_op_rate 164458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5776457310 # Simulator tick rate (ticks/s)
+host_mem_usage 314484 # Number of bytes of host memory used
+host_seconds 321.83 # Real time elapsed on the host
sim_insts 52927600 # Number of instructions simulated
sim_ops 52927600 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 13:11:51
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:24:03
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
sim_ticks 1841612450000 # Number of ticks simulated
final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 216403 # Simulator instruction rate (inst/s)
-host_op_rate 216403 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6103470891 # Simulator tick rate (ticks/s)
-host_mem_usage 319676 # Number of bytes of host memory used
-host_seconds 301.73 # Real time elapsed on the host
+host_inst_rate 223623 # Simulator instruction rate (inst/s)
+host_op_rate 223623 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6307109470 # Simulator tick rate (ticks/s)
+host_mem_usage 313464 # Number of bytes of host memory used
+host_seconds 291.99 # Real time elapsed on the host
sim_insts 65295558 # Number of instructions simulated
sim_ops 65295558 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60157.282465 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60157.282465 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.vram system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 12:48:24
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:01:45
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu0.isa: ISA system set to: 0x15f94710 0x15f94710
- 0: system.cpu1.isa: ISA system set to: 0x15f94710 0x15f94710
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu0.isa: ISA system set to: 0x40cab00 0x40cab00
+ 0: system.cpu1.isa: ISA system set to: 0x40cab00 0x40cab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1146870140500 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2843718094000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.658488 # Number of seconds simulated
-sim_ticks 2658488068000 # Number of ticks simulated
-final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.843718 # Number of seconds simulated
+sim_ticks 2843718094000 # Number of ticks simulated
+final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70694 # Simulator instruction rate (inst/s)
-host_op_rate 85127 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2981704600 # Simulator tick rate (ticks/s)
-host_mem_usage 438480 # Number of bytes of host memory used
-host_seconds 891.60 # Real time elapsed on the host
-sim_insts 63030433 # Number of instructions simulated
-sim_ops 75898814 # Number of ops (including micro ops) simulated
+host_inst_rate 161241 # Simulator instruction rate (inst/s)
+host_op_rate 195251 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3650642703 # Simulator tick rate (ticks/s)
+host_mem_usage 606904 # Number of bytes of host memory used
+host_seconds 778.96 # Real time elapsed on the host
+sim_insts 125601128 # Number of instructions simulated
+sim_ops 152093417 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15512805 # Number of read requests accepted
-system.physmem.writeReqs 825159 # Number of write requests accepted
-system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 969393 # Per bank write bursts
-system.physmem.perBankRdBursts::1 969270 # Per bank write bursts
-system.physmem.perBankRdBursts::2 969024 # Per bank write bursts
-system.physmem.perBankRdBursts::3 969581 # Per bank write bursts
-system.physmem.perBankRdBursts::4 971912 # Per bank write bursts
-system.physmem.perBankRdBursts::5 969565 # Per bank write bursts
-system.physmem.perBankRdBursts::6 969152 # Per bank write bursts
-system.physmem.perBankRdBursts::7 969036 # Per bank write bursts
-system.physmem.perBankRdBursts::8 969555 # Per bank write bursts
-system.physmem.perBankRdBursts::9 969606 # Per bank write bursts
-system.physmem.perBankRdBursts::10 969469 # Per bank write bursts
-system.physmem.perBankRdBursts::11 968910 # Per bank write bursts
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+system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue
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+system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side
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+system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2658486560500 # Total gap between requests
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+system.physmem.totGap 2843715756500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads
-system.physmem.totQLat 404032545000 # Total ticks spent queuing
-system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst
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+system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads
+system.physmem.totQLat 7621074500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.94 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 14503540 # Number of row buffer hits during reads
-system.physmem.writeRowHits 85448 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes
-system.physmem.avgGap 162718.35 # Average gap between requests
-system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states
-system.physmem.memoryStateTime::REF 88772580000 # Time in different power states
+system.physmem.busUtil 0.06 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing
+system.physmem.readRowHits 183248 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89836 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes
+system.physmem.avgGap 7693723.89 # Average gap between requests
+system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states
+system.physmem.memoryStateTime::REF 94957980000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states
+system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ)
-system.physmem.averagePower::0 697.245591 # Core power per rank (mW)
-system.physmem.averagePower::1 697.198662 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16692376 # Transaction distribution
-system.membus.trans_dist::ReadResp 16692376 # Transaction distribution
-system.membus.trans_dist::WriteReq 768869 # Transaction distribution
-system.membus.trans_dist::WriteResp 768869 # Transaction distribution
-system.membus.trans_dist::Writeback 67875 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution
-system.membus.trans_dist::ReadExReq 15293 # Transaction distribution
-system.membus.trans_dist::ReadExResp 8420 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 68687 # Total snoops (count)
-system.membus.snoop_fanout::samples 327086 # Request fanout histogram
+system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.547151 # Core power per rank (mW)
+system.physmem.averagePower::1 669.455073 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 238282 # Transaction distribution
+system.membus.trans_dist::ReadResp 238282 # Transaction distribution
+system.membus.trans_dist::WriteReq 31054 # Transaction distribution
+system.membus.trans_dist::WriteResp 31054 # Transaction distribution
+system.membus.trans_dist::Writeback 112138 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution
+system.membus.trans_dist::ReadExReq 30145 # Transaction distribution
+system.membus.trans_dist::ReadExResp 13182 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 124500 # Total snoops (count)
+system.membus.snoop_fanout::samples 499399 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 327086 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 499399 # Request fanout histogram
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 545180500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 10032364750 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.231255 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.142030 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.393701 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.426533 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.727850 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.472858 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.690476 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.877637 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817574 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.653397 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.841249 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.731482 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.405382 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.405382 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 170698 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 294957 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 31024 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31024 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7252165 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 34854856 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6449087 # DTB read hits
-system.cpu0.dtb.read_misses 22394 # DTB read misses
-system.cpu0.dtb.write_hits 5803603 # DTB write hits
-system.cpu0.dtb.write_misses 1784 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch
+system.cpu0.dtb.read_hits 23968692 # DTB read hits
+system.cpu0.dtb.read_misses 61651 # DTB read misses
+system.cpu0.dtb.write_hits 17871018 # DTB write hits
+system.cpu0.dtb.write_misses 6619 # DTB write misses
+system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6471481 # DTB read accesses
-system.cpu0.dtb.write_accesses 5805387 # DTB write accesses
+system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24030343 # DTB read accesses
+system.cpu0.dtb.write_accesses 17877637 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12252690 # DTB hits
-system.cpu0.dtb.misses 24178 # DTB misses
-system.cpu0.dtb.accesses 12276868 # DTB accesses
+system.cpu0.dtb.hits 41839710 # DTB hits
+system.cpu0.dtb.misses 68270 # DTB misses
+system.cpu0.dtb.accesses 41907980 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 13302311 # ITB inst hits
-system.cpu0.itb.inst_misses 3954 # ITB inst misses
+system.cpu0.itb.inst_hits 70097291 # ITB inst hits
+system.cpu0.itb.inst_misses 3844 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses
-system.cpu0.itb.hits 13302311 # DTB hits
-system.cpu0.itb.misses 3954 # DTB misses
-system.cpu0.itb.accesses 13306265 # DTB accesses
-system.cpu0.numCycles 86799146 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses
+system.cpu0.itb.hits 70097291 # DTB hits
+system.cpu0.itb.misses 3844 # DTB misses
+system.cpu0.itb.accesses 70101135 # DTB accesses
+system.cpu0.numCycles 227722348 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29471412 # Number of instructions committed
-system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.945198 # CPI: cycles per instruction
-system.cpu0.ipc 0.339536 # IPC: instructions per cycle
+system.cpu0.committedInsts 109201964 # Number of instructions committed
+system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.085332 # CPI: cycles per instruction
+system.cpu0.ipc 0.479540 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed
-system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped
-system.cpu0.icache.tags.replacements 670908 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
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+system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution
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+system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count)
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system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
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-system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram
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system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses
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-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063206 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency
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-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency
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-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency
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+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency
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+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 362294 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor
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-system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy
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+system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses
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-system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses
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-system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7012649 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits
+system.cpu1.branchPred.lookups 4191050 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7899300 # DTB read hits
-system.cpu1.dtb.read_misses 20789 # DTB read misses
-system.cpu1.dtb.write_hits 6047693 # DTB write hits
-system.cpu1.dtb.write_misses 2209 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch
+system.cpu1.dtb.read_hits 4177995 # DTB read hits
+system.cpu1.dtb.read_misses 21525 # DTB read misses
+system.cpu1.dtb.write_hits 3468676 # DTB write hits
+system.cpu1.dtb.write_misses 1889 # DTB write misses
+system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7920089 # DTB read accesses
-system.cpu1.dtb.write_accesses 6049902 # DTB write accesses
+system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 4199520 # DTB read accesses
+system.cpu1.dtb.write_accesses 3470565 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13946993 # DTB hits
-system.cpu1.dtb.misses 22998 # DTB misses
-system.cpu1.dtb.accesses 13969991 # DTB accesses
+system.cpu1.dtb.hits 7646671 # DTB hits
+system.cpu1.dtb.misses 23414 # DTB misses
+system.cpu1.dtb.accesses 7670085 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 14215184 # ITB inst hits
-system.cpu1.itb.inst_misses 5010 # ITB inst misses
+system.cpu1.itb.inst_hits 7954981 # ITB inst hits
+system.cpu1.itb.inst_misses 2237 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses
-system.cpu1.itb.hits 14215184 # DTB hits
-system.cpu1.itb.misses 5010 # DTB misses
-system.cpu1.itb.accesses 14220194 # DTB accesses
-system.cpu1.numCycles 502294457 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses
+system.cpu1.itb.hits 7954981 # DTB hits
+system.cpu1.itb.misses 2237 # DTB misses
+system.cpu1.itb.accesses 7957218 # DTB accesses
+system.cpu1.numCycles 42108230 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 33559021 # Number of instructions committed
-system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 14.967494 # CPI: cycles per instruction
-system.cpu1.ipc 0.066811 # IPC: instructions per cycle
+system.cpu1.committedInsts 16399164 # Number of instructions committed
+system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.567706 # CPI: cycles per instruction
+system.cpu1.ipc 0.389453 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed
-system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped
-system.cpu1.icache.tags.replacements 777492 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed
+system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped
+system.cpu1.icache.tags.replacements 921368 # number of replacements
+system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits
-system.cpu1.icache.overall_hits::total 13433657 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses
-system.cpu1.icache.overall_misses::total 778004 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits
+system.cpu1.icache.overall_hits::total 7030999 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses
+system.cpu1.icache.overall_misses::total 921880 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 606235 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 851885 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements 179644 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses
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-system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses
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-system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1004785618 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total 1004785618 # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11596750 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3042000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2529918546 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total 2544557296 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11596750 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3042000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2529918546 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total 2544557296 # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29788 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 987949 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 1025341 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks 242084 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total 242084 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20604 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 20604 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13688 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 13688 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 3 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136335 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 136335 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29788 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 1124284 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 1161676 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29788 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 1124284 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 1161676 # number of overall (read+write) accesses
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for overall accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18164.907783 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51692.257084 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16453.369157 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16453.369157 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14248.954190 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency
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-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency
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-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 322748 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 491.331318 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 11400815 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 323107 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 35.284952 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 72473667000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.331318 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959631 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.959631 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 24164293 # Number of tag accesses
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36445 # number of replacements
+system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328575 # Number of tag accesses
+system.iocache.tags.data_accesses 328575 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
+system.iocache.demand_misses::total 255 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 255 # number of overall misses
+system.iocache.overall_misses::total 255 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.vram system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: instruction 'mcr bpiall' unimplemented
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 17:07:27
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:01:02
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.isa: ISA system set to: 0x1a1f0030 0x1a1f0030
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x4defb00 0x4defb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2567809308500 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2852200332000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.566404 # Number of seconds simulated
-sim_ticks 2566404096500 # Number of ticks simulated
-final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.852200 # Number of seconds simulated
+sim_ticks 2852200332000 # Number of ticks simulated
+final_tick 2852200332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75271 # Simulator instruction rate (inst/s)
-host_op_rate 90613 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3188038304 # Simulator tick rate (ticks/s)
-host_mem_usage 412076 # Number of bytes of host memory used
-host_seconds 805.01 # Real time elapsed on the host
-sim_insts 60593541 # Number of instructions simulated
-sim_ops 72944224 # Number of ops (including micro ops) simulated
+host_inst_rate 169178 # Simulator instruction rate (inst/s)
+host_op_rate 204545 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4322499487 # Simulator tick rate (ticks/s)
+host_mem_usage 558640 # Number of bytes of host memory used
+host_seconds 659.85 # Real time elapsed on the host
+sim_insts 111631963 # Number of instructions simulated
+sim_ops 134968701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 6592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 10875428 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10883108 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1665536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1665536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5669632 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8005492 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15296370 # Number of read requests accepted
-system.physmem.writeReqs 813557 # Number of write requests accepted
-system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1646 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4678 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955907 # Per bank write bursts
-system.physmem.perBankRdBursts::1 955585 # Per bank write bursts
-system.physmem.perBankRdBursts::2 955711 # Per bank write bursts
-system.physmem.perBankRdBursts::3 955918 # Per bank write bursts
-system.physmem.perBankRdBursts::4 957666 # Per bank write bursts
-system.physmem.perBankRdBursts::5 955713 # Per bank write bursts
-system.physmem.perBankRdBursts::6 955586 # Per bank write bursts
-system.physmem.perBankRdBursts::7 955417 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956298 # Per bank write bursts
-system.physmem.perBankRdBursts::9 955963 # Per bank write bursts
-system.physmem.perBankRdBursts::10 955537 # Per bank write bursts
-system.physmem.perBankRdBursts::11 955091 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956282 # Per bank write bursts
-system.physmem.perBankRdBursts::13 955994 # Per bank write bursts
-system.physmem.perBankRdBursts::14 956147 # Per bank write bursts
-system.physmem.perBankRdBursts::15 955909 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6629 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6411 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6529 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6576 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6489 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6741 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6778 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6680 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7055 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6798 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6471 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6090 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7091 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6663 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6989 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6847 # Per bank write bursts
+system.physmem.num_reads::cpu.inst 170448 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 170568 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 88588 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 129193 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 2311 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 3812996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3815688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 583948 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 583948 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1987810 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 812824 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2806778 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1987810 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 813160 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2311 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3819140 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6622466 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170568 # Number of read requests accepted
+system.physmem.writeReqs 129193 # Number of write requests accepted
+system.physmem.readBursts 170568 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 129193 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10907008 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8019264 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10883108 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8005492 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4599 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10529 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10427 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10726 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10519 # Per bank write bursts
+system.physmem.perBankRdBursts::4 13519 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10191 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11164 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10885 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10359 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10882 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10112 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9441 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10326 # Per bank write bursts
+system.physmem.perBankRdBursts::13 11222 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10031 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10089 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7745 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7827 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8372 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8091 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7875 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7401 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8203 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8042 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7896 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8173 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7527 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7251 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7760 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8405 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7350 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7383 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2566402308000 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 2852199845000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 18 # Read request sizes (log2)
-system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
+system.physmem.readPktSize::2 541 # Read request sizes (log2)
+system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 157526 # Read request sizes (log2)
+system.physmem.readPktSize::6 170013 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 754018 # Write request sizes (log2)
+system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 59539 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1111407 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 958360 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 963566 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1076065 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 974438 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1039000 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12 100054 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14 18516 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 177 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 124812 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 163493 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6879 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6214 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22531 2.22% 4.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8793 0.87% 5.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1763 0.17% 5.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8722 0.86% 6.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 969 0.10% 6.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6195 99.90% 99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6201 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.980358 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2397 38.66% 38.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 13 0.21% 38.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 16 0.26% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 3 0.05% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads
-system.physmem.totQLat 395011426750 # Total ticks spent queuing
-system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15 1958 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2501 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 60576 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 312.437401 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 184.644234 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 330.251922 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22086 36.46% 36.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14485 23.91% 60.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6694 11.05% 71.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3534 5.83% 77.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2501 4.13% 81.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1624 2.68% 84.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1087 1.79% 85.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7503 12.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 60576 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6291 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 27.088221 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 577.877413 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6289 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6291 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6291 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.917501 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.380102 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.942111 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5514 87.65% 87.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 46 0.73% 88.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.49% 88.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 207 3.29% 92.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 183 2.91% 95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 14 0.22% 95.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 17 0.27% 95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 17 0.27% 95.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 30 0.48% 96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 7 0.11% 96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 3 0.05% 96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 154 2.45% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.05% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 2 0.03% 99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 4 0.06% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 21 0.33% 99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 3 0.05% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 6 0.10% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 3 0.05% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 2 0.03% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 2 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6291 # Writes before turning the bus around for reads
+system.physmem.totQLat 1680738000 # Total ticks spent queuing
+system.physmem.totMemAccLat 4876150500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 852110000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9862.21 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28612.21 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.00 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
-system.physmem.readRowHits 14297539 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89444 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes
-system.physmem.avgGap 159305.64 # Average gap between requests
-system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states
-system.physmem.memoryStateTime::REF 85697820000 # Time in different power states
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing
+system.physmem.readRowHits 140727 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94419 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.34 # Row buffer hit rate for writes
+system.physmem.avgGap 9514913.03 # Average gap between requests
+system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2713226080000 # Time in different power states
+system.physmem.memoryStateTime::REF 95241120000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states
+system.physmem.memoryStateTime::ACT 43733042000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3833766720 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3836442960 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2091837000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2093297250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 59650523400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 59648323800 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 342357840 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 349945920 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 167624935920 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 167624935920 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 149819559525 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 149631019200 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1408420983750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1408586370000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1791783964155 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1791770335050 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.169437 # Core power per rank (mW)
-system.physmem.averagePower::1 698.164127 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 16348869 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348869 # Transaction distribution
-system.membus.trans_dist::WriteReq 763365 # Transaction distribution
-system.membus.trans_dist::WriteResp 763365 # Transaction distribution
-system.membus.trans_dist::Writeback 59539 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4678 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131592 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131592 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 219423 # Request fanout histogram
+system.physmem.actEnergy::0 234125640 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 127747125 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 686088000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 643195800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 411842880 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 400107600 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 186291630720 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 186291630720 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 82872817560 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 82165704345 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1638622788000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1639243062750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1909247039925 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1909089659010 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.395204 # Core power per rank (mW)
+system.physmem.averagePower::1 669.340025 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 180 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 180 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 180 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 180 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 180 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 180 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 71824 # Transaction distribution
+system.membus.trans_dist::ReadResp 71824 # Transaction distribution
+system.membus.trans_dist::WriteReq 27607 # Transaction distribution
+system.membus.trans_dist::WriteResp 27607 # Transaction distribution
+system.membus.trans_dist::Writeback 88588 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4597 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129554 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129554 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 627985 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16569304 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16733149 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19052445 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 219 # Total snoops (count)
+system.membus.snoop_fanout::samples 296652 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 296652 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 219423 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 296652 # Request fanout histogram
+system.membus.reqLayer0.occupancy 87220000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1713500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1383760500 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1715299901 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38332500 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8178 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8178 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36805500 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 12550628 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits
+system.cpu.branchPred.lookups 30761849 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16759561 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2494541 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18376022 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13249221 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.100594 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7712174 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1491943 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13629467 # DTB read hits
-system.cpu.dtb.read_misses 33605 # DTB read misses
-system.cpu.dtb.write_hits 11376627 # DTB write hits
-system.cpu.dtb.write_misses 3703 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_hits 24631139 # DTB read hits
+system.cpu.dtb.read_misses 58263 # DTB read misses
+system.cpu.dtb.write_hits 19400231 # DTB write hits
+system.cpu.dtb.write_misses 6058 # DTB write misses
+system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4344 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1249 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 13663072 # DTB read accesses
-system.cpu.dtb.write_accesses 11380330 # DTB write accesses
+system.cpu.dtb.perms_faults 740 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24689402 # DTB read accesses
+system.cpu.dtb.write_accesses 19406289 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 25006094 # DTB hits
-system.cpu.dtb.misses 37308 # DTB misses
-system.cpu.dtb.accesses 25043402 # DTB accesses
+system.cpu.dtb.hits 44031370 # DTB hits
+system.cpu.dtb.misses 64321 # DTB misses
+system.cpu.dtb.accesses 44095691 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 22908933 # ITB inst hits
-system.cpu.itb.inst_misses 9079 # ITB inst misses
+system.cpu.itb.inst_hits 57062578 # ITB inst hits
+system.cpu.itb.inst_misses 5424 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2982 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8630 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 22918012 # ITB inst accesses
-system.cpu.itb.hits 22908933 # DTB hits
-system.cpu.itb.misses 9079 # DTB misses
-system.cpu.itb.accesses 22918012 # DTB accesses
-system.cpu.numCycles 572551547 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 57068002 # ITB inst accesses
+system.cpu.itb.hits 57062578 # DTB hits
+system.cpu.itb.misses 5424 # DTB misses
+system.cpu.itb.accesses 57068002 # DTB accesses
+system.cpu.numCycles 313219225 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60593541 # Number of instructions committed
-system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 9.449052 # CPI: cycles per instruction
-system.cpu.ipc 0.105831 # IPC: instructions per cycle
+system.cpu.committedInsts 111631963 # Number of instructions committed
+system.cpu.committedOps 134968701 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 7932752 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles 5391228164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.805820 # CPI: cycles per instruction
+system.cpu.ipc 0.356402 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed
-system.cpu.tickCycles 466653116 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 105898431 # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements 1529478 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.463685 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 21373010 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1529990 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 13.969379 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 9990881000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.463685 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.998953 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.998953 # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
+system.cpu.tickCycles 224159041 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 89060184 # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements 2896816 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.427908 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 54156207 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 2897328 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18.691776 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 15213008250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.427908 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 24432991 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 24432991 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 21373010 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 21373010 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 21373010 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 21373010 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 21373010 # number of overall hits
-system.cpu.icache.overall_hits::total 21373010 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1529991 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1529991 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1529991 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1529991 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1529991 # number of overall misses
-system.cpu.icache.overall_misses::total 1529991 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 20681368889 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 20681368889 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 20681368889 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 20681368889 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 20681368889 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 20681368889 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22903001 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 22903001 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 22903001 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 22903001 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 22903001 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 22903001 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066803 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.066803 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.066803 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.066803 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.066803 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13517.314082 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13517.314082 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 59950884 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 59950884 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 54156207 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 54156207 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 54156207 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 54156207 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 54156207 # number of overall hits
+system.cpu.icache.overall_hits::total 54156207 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 2897339 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 2897339 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 2897339 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 2897339 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 2897339 # number of overall misses
+system.cpu.icache.overall_misses::total 2897339 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 39126605503 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 39126605503 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 39126605503 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 39126605503 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 39126605503 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 39126605503 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 57053546 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 57053546 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 57053546 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 57053546 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 57053546 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 57053546 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050783 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.050783 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.050783 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.050783 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.050783 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.050783 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13504.324314 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13504.324314 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529991 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1529991 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1529991 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1529991 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1529991 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1529991 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17615727111 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 17615727111 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17615727111 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 17615727111 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17615727111 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 17615727111 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172140750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172140750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172140750 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 172140750 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066803 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.066803 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.066803 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.toL2Bus.trans_dist::ReadResp 3182061 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::UpgradeResp 2980 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247461 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247461 # Transaction distribution
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-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 2846983 100.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
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+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
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+system.cpu.dcache.overall_mshr_miss_rate::total 0.019564 # mshr miss rate for overall accesses
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+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253 # average LoadLockedReq mshr miss latency
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+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36424 # number of replacements
+system.iocache.tags.tagsinuse 1.031370 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 269945589000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.031370 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328122 # Number of tag accesses
+system.iocache.tags.data_accesses 328122 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
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+system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
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+system.iocache.overall_miss_latency::total 27970377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
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+system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
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+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119531.525641 # average ReadReq miss latency
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+system.iocache.overall_avg_miss_latency::total 119531.525641 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
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+system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
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+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2215530472 # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 15801377 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 15801377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.checker.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
-warn: LCD dual screen mode not supported
-warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
-warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
-warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
-warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
-warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: 8445832500: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+warn: 81667444500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: Returning zero for read from miscreg pmcr
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcr
+warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0]
+warn: 404836653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: instruction 'mcr bpiall' unimplemented
+warn: instruction 'mcr dcisw' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:27:42
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:12:13
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990
- 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.checker.isa: ISA system set to: 0x59c2b00 0x59c2b00
+ 0: system.cpu.isa: ISA system set to: 0x59c2b00 0x59c2b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2525888859000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2826845674500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542157 # Number of seconds simulated
-sim_ticks 2542156879500 # Number of ticks simulated
-final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.826846 # Number of seconds simulated
+sim_ticks 2826845674500 # Number of ticks simulated
+final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45837 # Simulator instruction rate (inst/s)
-host_op_rate 55223 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1932040285 # Simulator tick rate (ticks/s)
-host_mem_usage 415140 # Number of bytes of host memory used
-host_seconds 1315.79 # Real time elapsed on the host
-sim_insts 60311972 # Number of instructions simulated
-sim_ops 72661518 # Number of ops (including micro ops) simulated
+host_inst_rate 73722 # Simulator instruction rate (inst/s)
+host_op_rate 89421 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1841455705 # Simulator tick rate (ticks/s)
+host_mem_usage 559660 # Number of bytes of host memory used
+host_seconds 1535.11 # Real time elapsed on the host
+sim_insts 113172343 # Number of instructions simulated
+sim_ops 137271263 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15295608 # Number of read requests accepted
-system.physmem.writeReqs 812506 # Number of write requests accepted
-system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955787 # Per bank write bursts
-system.physmem.perBankRdBursts::1 955478 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953511 # Per bank write bursts
-system.physmem.perBankRdBursts::3 951566 # Per bank write bursts
-system.physmem.perBankRdBursts::4 958612 # Per bank write bursts
-system.physmem.perBankRdBursts::5 955530 # Per bank write bursts
-system.physmem.perBankRdBursts::6 953056 # Per bank write bursts
-system.physmem.perBankRdBursts::7 951020 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956158 # Per bank write bursts
-system.physmem.perBankRdBursts::9 955874 # Per bank write bursts
-system.physmem.perBankRdBursts::10 952686 # Per bank write bursts
-system.physmem.perBankRdBursts::11 950200 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956166 # Per bank write bursts
-system.physmem.perBankRdBursts::13 955918 # Per bank write bursts
-system.physmem.perBankRdBursts::14 953812 # Per bank write bursts
-system.physmem.perBankRdBursts::15 951254 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6556 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6344 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6481 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6512 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6422 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6709 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6691 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6631 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6968 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6764 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6424 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6068 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7033 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6638 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6915 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6799 # Per bank write bursts
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 172183 # Number of read requests accepted
+system.physmem.writeReqs 131246 # Number of write requests accepted
+system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10992 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10130 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11200 # Per bank write bursts
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-system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
-system.physmem.totQLat 395458190750 # Total ticks spent queuing
-system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads
+system.physmem.totQLat 2068507750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
-system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
-system.physmem.avgGap 157818.32 # Average gap between requests
-system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
-system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing
+system.physmem.readRowHits 142034 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95196 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes
+system.physmem.avgGap 9316332.35 # Average gap between requests
+system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states
+system.physmem.memoryStateTime::REF 94394560000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
+system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.235540 # Core power per rank (mW)
-system.physmem.averagePower::1 698.237375 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
-system.membus.trans_dist::WriteReq 763357 # Transaction distribution
-system.membus.trans_dist::WriteResp 763357 # Transaction distribution
-system.membus.trans_dist::Writeback 58488 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 216513 # Request fanout histogram
+system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.338580 # Core power per rank (mW)
+system.physmem.averagePower::1 669.240432 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 67851 # Transaction distribution
+system.membus.trans_dist::ReadResp 67850 # Transaction distribution
+system.membus.trans_dist::WriteReq 27608 # Transaction distribution
+system.membus.trans_dist::WriteResp 27608 # Transaction distribution
+system.membus.trans_dist::Writeback 90641 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135128 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135128 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 205 # Total snoops (count)
+system.membus.snoop_fanout::samples 300256 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 216513 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 300256 # Request fanout histogram
+system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59035 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 13200672 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
+system.cpu.branchPred.lookups 46931803 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 13156766 # DTB read hits
-system.cpu.checker.dtb.read_misses 7319 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227349 # DTB write hits
-system.cpu.checker.dtb.write_misses 2193 # DTB write misses
-system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.read_hits 24593793 # DTB read hits
+system.cpu.checker.dtb.read_misses 8242 # DTB read misses
+system.cpu.checker.dtb.write_hits 19641565 # DTB write hits
+system.cpu.checker.dtb.write_misses 1441 # DTB write misses
+system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
+system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
+system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries 4295 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses
+system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses 24602035 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 19643006 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 24384115 # DTB hits
-system.cpu.checker.dtb.misses 9512 # DTB misses
-system.cpu.checker.dtb.accesses 24393627 # DTB accesses
+system.cpu.checker.dtb.hits 44235358 # DTB hits
+system.cpu.checker.dtb.misses 9683 # DTB misses
+system.cpu.checker.dtb.accesses 44245041 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits
-system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
+system.cpu.checker.itb.inst_hits 115874779 # ITB inst hits
+system.cpu.checker.itb.inst_misses 4826 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
-system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
+system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries 2977 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses
-system.cpu.checker.itb.hits 61486106 # DTB hits
-system.cpu.checker.itb.misses 4473 # DTB misses
-system.cpu.checker.itb.accesses 61490579 # DTB accesses
-system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 115879605 # ITB inst accesses
+system.cpu.checker.itb.hits 115874779 # DTB hits
+system.cpu.checker.itb.misses 4826 # DTB misses
+system.cpu.checker.itb.accesses 115879605 # DTB accesses
+system.cpu.checker.numCycles 139125744 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31644036 # DTB read hits
-system.cpu.dtb.read_misses 39518 # DTB read misses
-system.cpu.dtb.write_hits 11381434 # DTB write hits
-system.cpu.dtb.write_misses 10146 # DTB write misses
-system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_hits 25464394 # DTB read hits
+system.cpu.dtb.read_misses 60419 # DTB read misses
+system.cpu.dtb.write_hits 19915991 # DTB write hits
+system.cpu.dtb.write_misses 9380 # DTB write misses
+system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31683554 # DTB read accesses
-system.cpu.dtb.write_accesses 11391580 # DTB write accesses
+system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25524813 # DTB read accesses
+system.cpu.dtb.write_accesses 19925371 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 43025470 # DTB hits
-system.cpu.dtb.misses 49664 # DTB misses
-system.cpu.dtb.accesses 43075134 # DTB accesses
+system.cpu.dtb.hits 45380385 # DTB hits
+system.cpu.dtb.misses 69799 # DTB misses
+system.cpu.dtb.accesses 45450184 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 24158829 # ITB inst hits
-system.cpu.itb.inst_misses 10513 # ITB inst misses
+system.cpu.itb.inst_hits 66292387 # ITB inst hits
+system.cpu.itb.inst_misses 11931 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
-system.cpu.itb.hits 24158829 # DTB hits
-system.cpu.itb.misses 10513 # DTB misses
-system.cpu.itb.accesses 24169342 # DTB accesses
-system.cpu.numCycles 499362415 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66304318 # ITB inst accesses
+system.cpu.itb.hits 66292387 # DTB hits
+system.cpu.itb.misses 11931 # DTB misses
+system.cpu.itb.accesses 66304318 # DTB accesses
+system.cpu.numCycles 260551438 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle
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+system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking
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+system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch
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+system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking
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+system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full
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+system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups
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+system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed
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+system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores.
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+system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued
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+system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
-system.cpu.iq.rate 0.188049 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued
+system.cpu.iq.rate 0.550119 # Inst issue rate
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+system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 176011 # number of nop insts executed
-system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10791373 # Number of branches executed
-system.cpu.iew.exec_stores 11888962 # Number of stores executed
-system.cpu.iew.exec_rate 0.186737 # Inst execution rate
-system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 35461894 # num instructions producing a value
-system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
+system.cpu.iew.exec_nop 200946 # number of nop insts executed
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+system.cpu.iew.exec_stores 20878795 # Number of stores executed
+system.cpu.iew.exec_rate 0.546502 # Inst execution rate
+system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63282838 # num instructions producing a value
+system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit
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+system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60462353 # Number of instructions committed
-system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113327248 # Number of instructions committed
+system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 25244590 # Number of memory references committed
-system.cpu.commit.loads 13512938 # Number of loads committed
-system.cpu.commit.membars 403660 # Number of memory barriers committed
-system.cpu.commit.branches 10308077 # Number of branches committed
-system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991634 # Number of function calls committed.
+system.cpu.commit.refs 45519928 # Number of memory references committed
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+system.cpu.commit.membars 814679 # Number of memory barriers committed
+system.cpu.commit.branches 26048896 # Number of branches committed
+system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 120245785 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4892513 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction
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+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60311972 # Number of Instructions Simulated
-system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
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-system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
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-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.rob.rob_reads 373356629 # The number of ROB reads
+system.cpu.rob.rob_writes 292965429 # The number of ROB writes
+system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.committedInsts 113172343 # Number of Instructions Simulated
+system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 155828809 # number of integer regfile reads
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+system.cpu.fp_regfile_reads 9591 # number of floating regfile reads
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+system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution
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+system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.snoops 65503 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9 2266210 100.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 959838 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks.
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-system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked
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+system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles
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+system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles
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+system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses
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+system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks
-system.cpu.dcache.writebacks::total 599947 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks
+system.cpu.dcache.writebacks::total 695424 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36410 # number of replacements
+system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328020 # Number of tag accesses
+system.iocache.tags.data_accesses 328020 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses
+system.iocache.demand_misses::total 220 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 220 # number of overall misses
+system.iocache.overall_misses::total 220 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: allocating bonus target for snoop
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: instruction 'mcr dcisw' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:27:42
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:14:43
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100
- 0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu0.isa: ISA system set to: 0x5555b00 0x5555b00
+ 0: system.cpu1.isa: ISA system set to: 0x5555b00 0x5555b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2605245500000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2824356167500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.607932 # Number of seconds simulated
-sim_ticks 2607931908500 # Number of ticks simulated
-final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.824356 # Number of seconds simulated
+sim_ticks 2824356167500 # Number of ticks simulated
+final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52184 # Simulator instruction rate (inst/s)
-host_op_rate 62850 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2168410643 # Simulator tick rate (ticks/s)
-host_mem_usage 492092 # Number of bytes of host memory used
-host_seconds 1202.69 # Real time elapsed on the host
-sim_insts 62761278 # Number of instructions simulated
-sim_ops 75589768 # Number of ops (including micro ops) simulated
+host_inst_rate 95847 # Simulator instruction rate (inst/s)
+host_op_rate 116283 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2253286315 # Simulator tick rate (ticks/s)
+host_mem_usage 605880 # Number of bytes of host memory used
+host_seconds 1253.44 # Real time elapsed on the host
+sim_insts 120137953 # Number of instructions simulated
+sim_ops 145753814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2607930021000 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 2824354558500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads
-system.physmem.totQLat 400005056750 # Total ticks spent queuing
-system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads
+system.physmem.totQLat 8921648500 # Total ticks spent queuing
+system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.95 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing
-system.physmem.readRowHits 14262971 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87526 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes
-system.physmem.avgGap 161548.30 # Average gap between requests
-system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states
-system.physmem.memoryStateTime::REF 87084400000 # Time in different power states
+system.physmem.busUtil 0.07 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing
+system.physmem.readRowHits 185257 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90003 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes
+system.physmem.avgGap 7586518.32 # Average gap between requests
+system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states
+system.physmem.memoryStateTime::REF 94311360000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states
+system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ)
-system.physmem.averagePower::0 697.255251 # Core power per rank (mW)
-system.physmem.averagePower::1 697.172828 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 16496763 # Transaction distribution
-system.membus.trans_dist::ReadResp 16496763 # Transaction distribution
-system.membus.trans_dist::WriteReq 769202 # Transaction distribution
-system.membus.trans_dist::WriteResp 769202 # Transaction distribution
-system.membus.trans_dist::Writeback 68618 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution
-system.membus.trans_dist::ReadExReq 15703 # Transaction distribution
-system.membus.trans_dist::ReadExResp 8933 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 177868 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 291850 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 31016 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31016 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 6445077 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 24027935 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6738270 # DTB read hits
-system.cpu0.dtb.read_misses 20792 # DTB read misses
-system.cpu0.dtb.write_hits 5108254 # DTB write hits
-system.cpu0.dtb.write_misses 4938 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
+system.cpu0.dtb.read_hits 17722520 # DTB read hits
+system.cpu0.dtb.read_misses 56371 # DTB read misses
+system.cpu0.dtb.write_hits 14647463 # DTB write hits
+system.cpu0.dtb.write_misses 8727 # DTB write misses
+system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6759062 # DTB read accesses
-system.cpu0.dtb.write_accesses 5113192 # DTB write accesses
+system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 17778891 # DTB read accesses
+system.cpu0.dtb.write_accesses 14656190 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 11846524 # DTB hits
-system.cpu0.dtb.misses 25730 # DTB misses
-system.cpu0.dtb.accesses 11872254 # DTB accesses
+system.cpu0.dtb.hits 32369983 # DTB hits
+system.cpu0.dtb.misses 65098 # DTB misses
+system.cpu0.dtb.accesses 32435081 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 11251934 # ITB inst hits
-system.cpu0.itb.inst_misses 5844 # ITB inst misses
+system.cpu0.itb.inst_hits 37749886 # ITB inst hits
+system.cpu0.itb.inst_misses 10298 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses
-system.cpu0.itb.hits 11251934 # DTB hits
-system.cpu0.itb.misses 5844 # DTB misses
-system.cpu0.itb.accesses 11257778 # DTB accesses
-system.cpu0.numCycles 70547986 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses
+system.cpu0.itb.hits 37749886 # DTB hits
+system.cpu0.itb.misses 10298 # DTB misses
+system.cpu0.itb.accesses 37760184 # DTB accesses
+system.cpu0.numCycles 126958641 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph
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+system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued
-system.cpu0.iq.rate 0.464855 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued
+system.cpu0.iq.rate 0.792936 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 102446 # number of nop insts executed
-system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4700114 # Number of branches executed
-system.cpu0.iew.exec_stores 5379801 # Number of stores executed
-system.cpu0.iew.exec_rate 0.459648 # Inst execution rate
-system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 15739944 # num instructions producing a value
-system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value
+system.cpu0.iew.exec_nop 174739 # number of nop insts executed
+system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 16843329 # Number of branches executed
+system.cpu0.iew.exec_stores 15534866 # Number of stores executed
+system.cpu0.iew.exec_rate 0.784292 # Inst execution rate
+system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 51320038 # num instructions producing a value
+system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24068410 # Number of instructions committed
-system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 78900966 # Number of instructions committed
+system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 10570507 # Number of memory references committed
-system.cpu0.commit.loads 5342633 # Number of loads committed
-system.cpu0.commit.membars 231974 # Number of memory barriers committed
-system.cpu0.commit.branches 4351471 # Number of branches committed
-system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 499778 # Number of function calls committed.
+system.cpu0.commit.refs 31909485 # Number of memory references committed
+system.cpu0.commit.loads 16729098 # Number of loads committed
+system.cpu0.commit.membars 647159 # Number of memory barriers committed
+system.cpu0.commit.branches 16205509 # Number of branches committed
+system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 1929583 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 99997744 # The number of ROB reads
-system.cpu0.rob.rob_writes 65895627 # The number of ROB writes
-system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23987668 # Number of Instructions Simulated
-system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads
-system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 840 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes
-system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 640729 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram
+system.cpu0.rob.rob_reads 221353668 # The number of ROB reads
+system.cpu0.rob.rob_writes 208668086 # The number of ROB writes
+system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 78778915 # Number of Instructions Simulated
+system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads
+system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes
+system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution
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+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes)
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+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count)
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system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram
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system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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+system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 322116 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page
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system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id
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-system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency
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-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks
+system.cpu0.dcache.writebacks::total 512498 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9149866 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits
+system.cpu1.branchPred.lookups 33913093 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25102636 # DTB read hits
-system.cpu1.dtb.read_misses 30137 # DTB read misses
-system.cpu1.dtb.write_hits 6841685 # DTB write hits
-system.cpu1.dtb.write_misses 6769 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
+system.cpu1.dtb.read_hits 10162981 # DTB read hits
+system.cpu1.dtb.read_misses 18754 # DTB read misses
+system.cpu1.dtb.write_hits 6542585 # DTB write hits
+system.cpu1.dtb.write_misses 2848 # DTB write misses
+system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25132773 # DTB read accesses
-system.cpu1.dtb.write_accesses 6848454 # DTB write accesses
+system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 10181735 # DTB read accesses
+system.cpu1.dtb.write_accesses 6545433 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31944321 # DTB hits
-system.cpu1.dtb.misses 36906 # DTB misses
-system.cpu1.dtb.accesses 31981227 # DTB accesses
+system.cpu1.dtb.hits 16705566 # DTB hits
+system.cpu1.dtb.misses 21602 # DTB misses
+system.cpu1.dtb.accesses 16727168 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 16803682 # ITB inst hits
-system.cpu1.itb.inst_misses 6173 # ITB inst misses
+system.cpu1.itb.inst_hits 43643100 # ITB inst hits
+system.cpu1.itb.inst_misses 6996 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses
-system.cpu1.itb.hits 16803682 # DTB hits
-system.cpu1.itb.misses 6173 # DTB misses
-system.cpu1.itb.accesses 16809855 # DTB accesses
-system.cpu1.numCycles 436917069 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses
+system.cpu1.itb.hits 43643100 # DTB hits
+system.cpu1.itb.misses 6996 # DTB misses
+system.cpu1.itb.accesses 43650096 # DTB accesses
+system.cpu1.numCycles 104633766 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph
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+system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued
-system.cpu1.iq.rate 0.149104 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued
+system.cpu1.iq.rate 0.515224 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 89541 # number of nop insts executed
-system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6846575 # Number of branches executed
-system.cpu1.iew.exec_stores 7146063 # Number of stores executed
-system.cpu1.iew.exec_rate 0.147981 # Inst execution rate
-system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 25811466 # num instructions producing a value
-system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value
+system.cpu1.iew.exec_nop 52145 # number of nop insts executed
+system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 11808497 # Number of branches executed
+system.cpu1.iew.exec_stores 6687543 # Number of stores executed
+system.cpu1.iew.exec_rate 0.512635 # Inst execution rate
+system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 25227303 # num instructions producing a value
+system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38843249 # Number of instructions committed
-system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 41391892 # Number of instructions committed
+system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 15740654 # Number of memory references committed
-system.cpu1.commit.loads 8748353 # Number of loads committed
-system.cpu1.commit.membars 195273 # Number of memory barriers committed
-system.cpu1.commit.branches 6419002 # Number of branches committed
-system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 553431 # Number of function calls committed.
+system.cpu1.commit.refs 16523842 # Number of memory references committed
+system.cpu1.commit.loads 9966044 # Number of loads committed
+system.cpu1.commit.membars 209647 # Number of memory barriers committed
+system.cpu1.commit.branches 11639863 # Number of branches committed
+system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 3366801 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 483317632 # The number of ROB reads
-system.cpu1.rob.rob_writes 101136219 # The number of ROB writes
-system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38773610 # Number of Instructions Simulated
-system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads
-system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes
-system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 595717 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram
+system.cpu1.rob.rob_reads 136568898 # The number of ROB reads
+system.cpu1.rob.rob_writes 111201426 # The number of ROB writes
+system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 41359038 # Number of Instructions Simulated
+system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads
+system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 520 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes
+system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 836156 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.icache.tags.replacements 546235 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 607230 # number of replacements
+system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits
-system.cpu1.icache.overall_hits::total 16238797 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses
-system.cpu1.icache.overall_misses::total 562244 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits
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+system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses
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+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles
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+system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency
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+system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 381661 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor
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-system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits
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-system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses
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-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses
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-system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency
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+system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy
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+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
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+system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses
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+system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits
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+system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits
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+system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 648286 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks
-system.cpu1.dcache.writebacks::total 291033 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks
+system.cpu1.dcache.writebacks::total 116918 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses
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+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36453 # number of replacements
+system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328407 # Number of tag accesses
+system.iocache.tags.data_accesses 328407 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 247 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses
+system.iocache.demand_misses::total 247 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 247 # number of overall misses
+system.iocache.overall_misses::total 247 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0]
+warn: instruction 'mcr bpiall' unimplemented
+warn: instruction 'mcr dcisw' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:27:42
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:06:55
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x5387b00 0x5387b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2525888859000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2826845674500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542157 # Number of seconds simulated
-sim_ticks 2542156879500 # Number of ticks simulated
-final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.826846 # Number of seconds simulated
+sim_ticks 2826845674500 # Number of ticks simulated
+final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53387 # Simulator instruction rate (inst/s)
-host_op_rate 64319 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2250271387 # Simulator tick rate (ticks/s)
-host_mem_usage 465820 # Number of bytes of host memory used
-host_seconds 1129.71 # Real time elapsed on the host
-sim_insts 60311972 # Number of instructions simulated
-sim_ops 72661518 # Number of ops (including micro ops) simulated
+host_inst_rate 98010 # Simulator instruction rate (inst/s)
+host_op_rate 118881 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2448127815 # Simulator tick rate (ticks/s)
+host_mem_usage 558668 # Number of bytes of host memory used
+host_seconds 1154.70 # Real time elapsed on the host
+sim_insts 113172343 # Number of instructions simulated
+sim_ops 137271263 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15295608 # Number of read requests accepted
-system.physmem.writeReqs 812506 # Number of write requests accepted
-system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955787 # Per bank write bursts
-system.physmem.perBankRdBursts::1 955478 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953511 # Per bank write bursts
-system.physmem.perBankRdBursts::3 951566 # Per bank write bursts
-system.physmem.perBankRdBursts::4 958612 # Per bank write bursts
-system.physmem.perBankRdBursts::5 955530 # Per bank write bursts
-system.physmem.perBankRdBursts::6 953056 # Per bank write bursts
-system.physmem.perBankRdBursts::7 951020 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956158 # Per bank write bursts
-system.physmem.perBankRdBursts::9 955874 # Per bank write bursts
-system.physmem.perBankRdBursts::10 952686 # Per bank write bursts
-system.physmem.perBankRdBursts::11 950200 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956166 # Per bank write bursts
-system.physmem.perBankRdBursts::13 955918 # Per bank write bursts
-system.physmem.perBankRdBursts::14 953812 # Per bank write bursts
-system.physmem.perBankRdBursts::15 951254 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6556 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6344 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6481 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6512 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6422 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6709 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6691 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6631 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6968 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6764 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6424 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6068 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7033 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6638 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6915 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6799 # Per bank write bursts
+system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 172183 # Number of read requests accepted
+system.physmem.writeReqs 131246 # Number of write requests accepted
+system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10992 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10130 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2542155562500 # Total gap between requests
+system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
+system.physmem.totGap 2826845408500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
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-system.physmem.readPktSize::2 18 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 153413 # Read request sizes (log2)
+system.physmem.readPktSize::6 168635 # Read request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
-system.physmem.totQLat 395458190750 # Total ticks spent queuing
-system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads
+system.physmem.totQLat 2068507750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
-system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
-system.physmem.avgGap 157818.32 # Average gap between requests
-system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
-system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing
+system.physmem.readRowHits 142034 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95196 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes
+system.physmem.avgGap 9316332.35 # Average gap between requests
+system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states
+system.physmem.memoryStateTime::REF 94394560000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
+system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.235540 # Core power per rank (mW)
-system.physmem.averagePower::1 698.237375 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
-system.membus.trans_dist::WriteReq 763357 # Transaction distribution
-system.membus.trans_dist::WriteResp 763357 # Transaction distribution
-system.membus.trans_dist::Writeback 58488 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 216513 # Request fanout histogram
+system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.338580 # Core power per rank (mW)
+system.physmem.averagePower::1 669.240432 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 67851 # Transaction distribution
+system.membus.trans_dist::ReadResp 67850 # Transaction distribution
+system.membus.trans_dist::WriteReq 27608 # Transaction distribution
+system.membus.trans_dist::WriteResp 27608 # Transaction distribution
+system.membus.trans_dist::Writeback 90641 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135128 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135128 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 205 # Total snoops (count)
+system.membus.snoop_fanout::samples 300256 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 216513 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 300256 # Request fanout histogram
+system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59035 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 13200672 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
+system.cpu.branchPred.lookups 46931803 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31644036 # DTB read hits
-system.cpu.dtb.read_misses 39518 # DTB read misses
-system.cpu.dtb.write_hits 11381434 # DTB write hits
-system.cpu.dtb.write_misses 10146 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_hits 25464394 # DTB read hits
+system.cpu.dtb.read_misses 60419 # DTB read misses
+system.cpu.dtb.write_hits 19915991 # DTB write hits
+system.cpu.dtb.write_misses 9380 # DTB write misses
+system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31683554 # DTB read accesses
-system.cpu.dtb.write_accesses 11391580 # DTB write accesses
+system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25524813 # DTB read accesses
+system.cpu.dtb.write_accesses 19925371 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 43025470 # DTB hits
-system.cpu.dtb.misses 49664 # DTB misses
-system.cpu.dtb.accesses 43075134 # DTB accesses
+system.cpu.dtb.hits 45380385 # DTB hits
+system.cpu.dtb.misses 69799 # DTB misses
+system.cpu.dtb.accesses 45450184 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 24158829 # ITB inst hits
-system.cpu.itb.inst_misses 10513 # ITB inst misses
+system.cpu.itb.inst_hits 66292387 # ITB inst hits
+system.cpu.itb.inst_misses 11931 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
-system.cpu.itb.hits 24158829 # DTB hits
-system.cpu.itb.misses 10513 # DTB misses
-system.cpu.itb.accesses 24169342 # DTB accesses
-system.cpu.numCycles 499362415 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66304318 # ITB inst accesses
+system.cpu.itb.hits 66292387 # DTB hits
+system.cpu.itb.misses 11931 # DTB misses
+system.cpu.itb.accesses 66304318 # DTB accesses
+system.cpu.numCycles 260551438 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
-system.cpu.iq.rate 0.188049 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued
+system.cpu.iq.rate 0.550119 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 176011 # number of nop insts executed
-system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10791373 # Number of branches executed
-system.cpu.iew.exec_stores 11888962 # Number of stores executed
-system.cpu.iew.exec_rate 0.186737 # Inst execution rate
-system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 35461894 # num instructions producing a value
-system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
+system.cpu.iew.exec_nop 200946 # number of nop insts executed
+system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26532601 # Number of branches executed
+system.cpu.iew.exec_stores 20878795 # Number of stores executed
+system.cpu.iew.exec_rate 0.546502 # Inst execution rate
+system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63282838 # num instructions producing a value
+system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60462353 # Number of instructions committed
-system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113327248 # Number of instructions committed
+system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 25244590 # Number of memory references committed
-system.cpu.commit.loads 13512938 # Number of loads committed
-system.cpu.commit.membars 403660 # Number of memory barriers committed
-system.cpu.commit.branches 10308077 # Number of branches committed
-system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991634 # Number of function calls committed.
+system.cpu.commit.refs 45519928 # Number of memory references committed
+system.cpu.commit.loads 24920655 # Number of loads committed
+system.cpu.commit.membars 814679 # Number of memory barriers committed
+system.cpu.commit.branches 26048896 # Number of branches committed
+system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 120245785 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4892513 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 568215140 # The number of ROB reads
-system.cpu.rob.rob_writes 154414029 # The number of ROB writes
-system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60311972 # Number of Instructions Simulated
-system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 109116744 # number of integer regfile reads
-system.cpu.int_regfile_writes 47012206 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8305 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2780 # number of floating regfile writes
-system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads
-system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes
-system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.rob.rob_reads 373356629 # The number of ROB reads
+system.cpu.rob.rob_writes 292965429 # The number of ROB writes
+system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked
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+system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks
-system.cpu.dcache.writebacks::total 599947 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks
+system.cpu.dcache.writebacks::total 695424 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36410 # number of replacements
+system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328020 # Number of tag accesses
+system.iocache.tags.data_accesses 328020 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses
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+system.iocache.demand_misses::total 220 # number of demand (read+write) misses
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+system.iocache.overall_misses::total 220 # number of overall misses
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+system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles
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+system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles
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+system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses
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+system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.vram system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu2.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
+warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
+warn: instruction 'mcr bpiall' unimplemented
+warn: instruction 'mcr dcisw' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
+warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:27:42
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:14:55
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
- 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
- 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
+ 0: system.cpu0.isa: ISA system set to: 0x5395b00 0x5395b00
+ 0: system.cpu1.isa: ISA system set to: 0x5395b00 0x5395b00
+ 0: system.cpu2.isa: ISA system set to: 0x5395b00 0x5395b00
---------- Begin Simulation Statistics ----------
-sim_seconds 2.400978 # Number of seconds simulated
-sim_ticks 2400977890000 # Number of ticks simulated
-final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.817969 # Number of seconds simulated
+sim_ticks 2817968959500 # Number of ticks simulated
+final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 187249 # Simulator instruction rate (inst/s)
-host_op_rate 225312 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7454963168 # Simulator tick rate (ticks/s)
-host_mem_usage 414124 # Number of bytes of host memory used
-host_seconds 322.06 # Real time elapsed on the host
-sim_insts 60306316 # Number of instructions simulated
-sim_ops 72565030 # Number of ops (including micro ops) simulated
+host_inst_rate 310224 # Simulator instruction rate (inst/s)
+host_op_rate 376688 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6925358539 # Simulator tick rate (ticks/s)
+host_mem_usage 560716 # Number of bytes of host memory used
+host_seconds 406.91 # Real time elapsed on the host
+sim_insts 126231917 # Number of instructions simulated
+sim_ops 153276568 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 489736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6827544 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 79168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 799488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 187904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1451008 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124654688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 489736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 79168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 187904 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 756808 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3741376 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1144160 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1712392 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6757192 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13864 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 106706 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1237 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 12492 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2936 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 22672 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512303 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58459 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 286040 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 428098 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812413 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47821795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 203974 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2843651 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 32973 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 332984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 213 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 78261 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 604340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51918299 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 203974 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 32973 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 78261 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 315208 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1558272 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 476539 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 713206 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2814350 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1558272 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47821795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 203974 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3320191 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 32973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 399317 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 78261 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1317546 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54732649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 13446786 # Number of read requests accepted
-system.physmem.writeReqs 485691 # Number of write requests accepted
-system.physmem.readBursts 13446786 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 485691 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 860594304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 3023744 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 109777664 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 3009384 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 438423 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 835534 # Per bank write bursts
-system.physmem.perBankRdBursts::1 835708 # Per bank write bursts
-system.physmem.perBankRdBursts::2 835573 # Per bank write bursts
-system.physmem.perBankRdBursts::3 835895 # Per bank write bursts
-system.physmem.perBankRdBursts::4 836820 # Per bank write bursts
-system.physmem.perBankRdBursts::5 838059 # Per bank write bursts
-system.physmem.perBankRdBursts::6 838590 # Per bank write bursts
-system.physmem.perBankRdBursts::7 839423 # Per bank write bursts
-system.physmem.perBankRdBursts::8 841113 # Per bank write bursts
-system.physmem.perBankRdBursts::9 843484 # Per bank write bursts
-system.physmem.perBankRdBursts::10 843775 # Per bank write bursts
-system.physmem.perBankRdBursts::11 843709 # Per bank write bursts
-system.physmem.perBankRdBursts::12 845212 # Per bank write bursts
-system.physmem.perBankRdBursts::13 845578 # Per bank write bursts
-system.physmem.perBankRdBursts::14 844651 # Per bank write bursts
-system.physmem.perBankRdBursts::15 843662 # Per bank write bursts
-system.physmem.perBankWrBursts::0 2614 # Per bank write bursts
-system.physmem.perBankWrBursts::1 2619 # Per bank write bursts
-system.physmem.perBankWrBursts::2 2845 # Per bank write bursts
-system.physmem.perBankWrBursts::3 3084 # Per bank write bursts
-system.physmem.perBankWrBursts::4 3522 # Per bank write bursts
-system.physmem.perBankWrBursts::5 3545 # Per bank write bursts
-system.physmem.perBankWrBursts::6 2950 # Per bank write bursts
-system.physmem.perBankWrBursts::7 2539 # Per bank write bursts
-system.physmem.perBankWrBursts::8 2638 # Per bank write bursts
-system.physmem.perBankWrBursts::9 2619 # Per bank write bursts
-system.physmem.perBankWrBursts::10 2391 # Per bank write bursts
-system.physmem.perBankWrBursts::11 2507 # Per bank write bursts
-system.physmem.perBankWrBursts::12 3740 # Per bank write bursts
-system.physmem.perBankWrBursts::13 3837 # Per bank write bursts
-system.physmem.perBankWrBursts::14 3267 # Per bank write bursts
-system.physmem.perBankWrBursts::15 2529 # Per bank write bursts
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+system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 92768 # Number of read requests accepted
+system.physmem.writeReqs 67796 # Number of write requests accepted
+system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 6044 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5813 # Per bank write bursts
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+system.physmem.perBankWrBursts::15 3898 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2398976781000 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
+system.physmem.totGap 2816402816000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 13407440 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 39346 # Read request sizes (log2)
+system.physmem.readPktSize::6 92767 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 467914 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 17777 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 878947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 855123 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::5 917283 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::1 95 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2025 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2612 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::19 2687 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21 2606 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 2682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 2704 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 2534 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 2534 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 2591 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 2515 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2520 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 2531 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 2487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8963 1.03% 1.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 764 0.09% 2.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7665 0.88% 3.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 291 0.03% 3.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 249325.060826 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 2587 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 2588 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 2588 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.255796 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.093626 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.104963 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1 2 0.08% 0.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 1 0.04% 0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3 3 0.12% 0.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4 1 0.04% 0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5 2 0.08% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7 3 0.12% 0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13 2 0.08% 0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14 2 0.08% 0.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 3 0.12% 0.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 555 21.45% 22.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 6 0.23% 22.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 738 28.52% 50.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1040 40.19% 91.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 103 3.98% 95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 50 1.93% 97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 14 0.54% 97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 11 0.43% 97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 13 0.50% 98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 5 0.19% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 7 0.27% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 6 0.23% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 5 0.19% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 6 0.23% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 4 0.15% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 5 0.19% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 1 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 2588 # Writes before turning the bus around for reads
-system.physmem.totQLat 347055171000 # Total ticks spent queuing
-system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst
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+system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads
+system.physmem.totQLat 1185317250 # Total ticks spent queuing
+system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.81 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 12587076 # Number of row buffer hits during reads
-system.physmem.writeRowHits 40794 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes
-system.physmem.avgGap 172185.95 # Average gap between requests
-system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states
-system.physmem.memoryStateTime::REF 80173860000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing
+system.physmem.readRowHits 76736 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50876 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
+system.physmem.avgGap 17540686.68 # Average gap between requests
+system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states
+system.physmem.memoryStateTime::REF 94098160000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states
+system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3260847240 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3287337480 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 1779232125 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 1793686125 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 52225695600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 52659235200 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 153692640 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 152461440 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 156820070160 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 156820070160 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 104351437575 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 103839738030 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1349049300750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1349498160000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1667640276090 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1668050688435 # Total energy per rank (pJ)
-system.physmem.averagePower::0 694.567634 # Core power per rank (mW)
-system.physmem.averagePower::1 694.738569 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 15564561 # Transaction distribution
-system.membus.trans_dist::ReadResp 15564561 # Transaction distribution
-system.membus.trans_dist::WriteReq 763190 # Transaction distribution
-system.membus.trans_dist::WriteResp 763190 # Transaction distribution
-system.membus.trans_dist::Writeback 58459 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131741 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131741 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3510 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7020 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16592808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18990169 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 114819072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 114819072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 133809241 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 216296 # Request fanout histogram
+system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.683537 # Core power per rank (mW)
+system.physmem.averagePower::1 668.631072 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 74237 # Transaction distribution
+system.membus.trans_dist::ReadResp 74236 # Transaction distribution
+system.membus.trans_dist::WriteReq 27571 # Transaction distribution
+system.membus.trans_dist::WriteResp 27571 # Transaction distribution
+system.membus.trans_dist::Writeback 92896 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137042 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137042 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 125 # Total snoops (count)
+system.membus.snoop_fanout::samples 304844 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 216296 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989189 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.963834 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.516781 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420225 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525365 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.258007 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530 # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 18229 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 51755 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution
-system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8154 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8154 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
+system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390317 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 114819072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 114819072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 117209389 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 8534000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 1569000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 352708000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 13407440000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 717460000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 33785464750 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6552093 # DTB read hits
-system.cpu0.dtb.read_misses 5443 # DTB read misses
-system.cpu0.dtb.write_hits 6067983 # DTB write hits
-system.cpu0.dtb.write_misses 1816 # DTB write misses
-system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5219 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits 14476225 # DTB read hits
+system.cpu0.dtb.read_misses 4878 # DTB read misses
+system.cpu0.dtb.write_hits 11074159 # DTB write hits
+system.cpu0.dtb.write_misses 931 # DTB write misses
+system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 108 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6557536 # DTB read accesses
-system.cpu0.dtb.write_accesses 6069799 # DTB write accesses
+system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 14481103 # DTB read accesses
+system.cpu0.dtb.write_accesses 11075090 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12620076 # DTB hits
-system.cpu0.dtb.misses 7259 # DTB misses
-system.cpu0.dtb.accesses 12627335 # DTB accesses
+system.cpu0.dtb.hits 25550384 # DTB hits
+system.cpu0.dtb.misses 5809 # DTB misses
+system.cpu0.dtb.accesses 25556193 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 30154576 # ITB inst hits
-system.cpu0.itb.inst_misses 2994 # ITB inst misses
+system.cpu0.itb.inst_hits 67954631 # ITB inst hits
+system.cpu0.itb.inst_misses 2810 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2367 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 30157570 # ITB inst accesses
-system.cpu0.itb.hits 30154576 # DTB hits
-system.cpu0.itb.misses 2994 # DTB misses
-system.cpu0.itb.accesses 30157570 # DTB accesses
-system.cpu0.numCycles 109411317 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses
+system.cpu0.itb.hits 67954631 # DTB hits
+system.cpu0.itb.misses 2810 # DTB misses
+system.cpu0.itb.accesses 67957441 # DTB accesses
+system.cpu0.numCycles 82556870 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29741333 # Number of instructions committed
-system.cpu0.committedOps 36475405 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 32123717 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses
-system.cpu0.num_func_calls 1120042 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3813280 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 32123717 # number of integer instructions
-system.cpu0.num_fp_insts 4289 # number of float instructions
-system.cpu0.num_int_register_reads 59486063 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 21170898 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 109224829 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 14221647 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13081203 # number of memory refs
-system.cpu0.num_load_insts 6727170 # Number of load instructions
-system.cpu0.num_store_insts 6354033 # Number of store instructions
-system.cpu0.num_idle_cycles 107121976.742744 # Number of idle cycles
-system.cpu0.num_busy_cycles 2289340.257256 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.020924 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.979076 # Percentage of idle cycles
-system.cpu0.Branches 5305474 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 11839 0.03% 0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu 23401650 64.04% 64.07% # Class of executed instruction
-system.cpu0.op_class::IntMult 45463 0.12% 64.20% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 1432 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu0.op_class::MemRead 6727170 18.41% 82.61% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6354033 17.39% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 66160123 # Number of instructions committed
+system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses
+system.cpu0.num_func_calls 7292026 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 70891568 # number of integer instructions
+system.cpu0.num_fp_insts 5582 # number of float instructions
+system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
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-system.cpu0.icache.demand_mshr_miss_rate::total 0.010828 # mshr miss rate for demand accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11751.868263 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use
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-system.cpu0.dcache.tags.avg_refs 33.828420 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.646695 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.878290 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
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-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65554993 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.WriteReq_accesses::cpu2.data 3266766 # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 32826 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 89090 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7098.651786 # average LoadLockedReq miss latency
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-system.cpu0.dcache.blocked_cycles::no_mshrs 35984 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 692569 # number of writebacks
+system.cpu0.dcache.writebacks::total 692569 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 109 # number of ReadReq MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_hits::total 155718 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total 1409743 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1933 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6811 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8744 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::cpu2.data 1565352 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1565461 # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 220193 # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 119815 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 153767 # number of WriteReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43915 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 63665 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1351 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2883 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4234 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 13 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.demand_mshr_misses::cpu2.data 280711 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 373960 # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::cpu2.data 324626 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 437625 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238573617 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777844500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1314970500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092815000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1797210500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3008091000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012184 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018081 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.007793 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014610 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020649 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 1733555 # DTB read hits
-system.cpu1.dtb.read_misses 1889 # DTB read misses
-system.cpu1.dtb.write_hits 1370998 # DTB write hits
-system.cpu1.dtb.write_misses 367 # DTB write misses
-system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1592 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits 4634872 # DTB read hits
+system.cpu1.dtb.read_misses 1584 # DTB read misses
+system.cpu1.dtb.write_hits 3276619 # DTB write hits
+system.cpu1.dtb.write_misses 228 # DTB write misses
+system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 28 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 1735444 # DTB read accesses
-system.cpu1.dtb.write_accesses 1371365 # DTB write accesses
+system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 4636456 # DTB read accesses
+system.cpu1.dtb.write_accesses 3276847 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3104553 # DTB hits
-system.cpu1.dtb.misses 2256 # DTB misses
-system.cpu1.dtb.accesses 3106809 # DTB accesses
+system.cpu1.dtb.hits 7911491 # DTB hits
+system.cpu1.dtb.misses 1812 # DTB misses
+system.cpu1.dtb.accesses 7913303 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 7924396 # ITB inst hits
-system.cpu1.itb.inst_misses 1030 # ITB inst misses
+system.cpu1.itb.inst_hits 21928102 # ITB inst hits
+system.cpu1.itb.inst_misses 848 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses
-system.cpu1.itb.hits 7924396 # DTB hits
-system.cpu1.itb.misses 1030 # DTB misses
-system.cpu1.itb.accesses 7925426 # DTB accesses
-system.cpu1.numCycles 582686408 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses
+system.cpu1.itb.hits 21928102 # DTB hits
+system.cpu1.itb.misses 848 # DTB misses
+system.cpu1.itb.accesses 21928950 # DTB accesses
+system.cpu1.numCycles 158012618 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7745878 # Number of instructions committed
-system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses
-system.cpu1.num_func_calls 287006 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 8166989 # number of integer instructions
-system.cpu1.num_fp_insts 1689 # number of float instructions
-system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written
-system.cpu1.num_mem_refs 3229777 # number of memory refs
-system.cpu1.num_load_insts 1791377 # Number of load instructions
-system.cpu1.num_store_insts 1438400 # Number of store instructions
-system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles
-system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles
-system.cpu1.Branches 1348409 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction
-system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction
-system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 21219740 # Number of instructions committed
+system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses
+system.cpu1.num_func_calls 2405283 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 22602371 # number of integer instructions
+system.cpu1.num_fp_insts 1626 # number of float instructions
+system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written
+system.cpu1.num_mem_refs 8126078 # number of memory refs
+system.cpu1.num_load_insts 4682102 # Number of load instructions
+system.cpu1.num_store_insts 3443976 # Number of store instructions
+system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles
+system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles
+system.cpu1.Branches 5257577 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction
+system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction
+system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 9282565 # Class of executed instruction
+system.cpu1.op_class::total 26134332 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 5846326 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits
+system.cpu2.branchPred.lookups 17411527 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 13911313 # DTB read hits
-system.cpu2.dtb.read_misses 27890 # DTB read misses
-system.cpu2.dtb.write_hits 3983127 # DTB write hits
-system.cpu2.dtb.write_misses 9793 # DTB write misses
-system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch
+system.cpu2.dtb.read_hits 9691496 # DTB read hits
+system.cpu2.dtb.read_misses 37543 # DTB read misses
+system.cpu2.dtb.write_hits 7160478 # DTB write hits
+system.cpu2.dtb.write_misses 5658 # DTB write misses
+system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 13939203 # DTB read accesses
-system.cpu2.dtb.write_accesses 3992920 # DTB write accesses
+system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 9729039 # DTB read accesses
+system.cpu2.dtb.write_accesses 7166136 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 17894440 # DTB hits
-system.cpu2.dtb.misses 37683 # DTB misses
-system.cpu2.dtb.accesses 17932123 # DTB accesses
+system.cpu2.dtb.hits 16851974 # DTB hits
+system.cpu2.dtb.misses 43201 # DTB misses
+system.cpu2.dtb.accesses 16895175 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.inst_hits 4060759 # ITB inst hits
-system.cpu2.itb.inst_misses 6577 # ITB inst misses
+system.cpu2.itb.inst_hits 12855360 # ITB inst hits
+system.cpu2.itb.inst_misses 6344 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 550 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses
-system.cpu2.itb.hits 4060759 # DTB hits
-system.cpu2.itb.misses 6577 # DTB misses
-system.cpu2.itb.accesses 4067336 # DTB accesses
-system.cpu2.numCycles 88050542 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses
+system.cpu2.itb.hits 12855360 # DTB hits
+system.cpu2.itb.misses 6344 # DTB misses
+system.cpu2.itb.accesses 12861704 # DTB accesses
+system.cpu2.numCycles 69831868 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued
-system.cpu2.iq.rate 0.438506 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued
+system.cpu2.iq.rate 0.744849 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 119730 # number of nop insts executed
-system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 4221740 # Number of branches executed
-system.cpu2.iew.exec_stores 4140164 # Number of stores executed
-system.cpu2.iew.exec_rate 0.434893 # Inst execution rate
-system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17270580 # num instructions producing a value
-system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value
+system.cpu2.iew.exec_nop 107408 # number of nop insts executed
+system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 9489180 # Number of branches executed
+system.cpu2.iew.exec_stores 7465028 # Number of stores executed
+system.cpu2.iew.exec_rate 0.738611 # Inst execution rate
+system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 26486298 # num instructions producing a value
+system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 22893469 # Number of instructions committed
-system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 38915831 # Number of instructions committed
+system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8921435 # Number of memory references committed
-system.cpu2.commit.loads 4987106 # Number of loads committed
-system.cpu2.commit.membars 117312 # Number of memory barriers committed
-system.cpu2.commit.branches 3648396 # Number of branches committed
-system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 341825 # Number of function calls committed.
+system.cpu2.commit.refs 15804910 # Number of memory references committed
+system.cpu2.commit.loads 8667813 # Number of loads committed
+system.cpu2.commit.membars 226604 # Number of memory barriers committed
+system.cpu2.commit.branches 8912074 # Number of branches committed
+system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 1635579 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 116684345 # The number of ROB reads
-system.cpu2.rob.rob_writes 65897015 # The number of ROB writes
-system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 22819105 # Number of Instructions Simulated
-system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads
-system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.cpu2.rob.rob_reads 113043839 # The number of ROB reads
+system.cpu2.rob.rob_writes 112575250 # The number of ROB writes
+system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 38852054 # Number of Instructions Simulated
+system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads
+system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes
+system.iocache.tags.replacements 36442 # number of replacements
+system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328356 # Number of tag accesses
+system.iocache.tags.data_accesses 328356 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
+system.iocache.demand_misses::total 252 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 252 # number of overall misses
+system.iocache.overall_misses::total 252 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.vram system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
+warn: CP14 unimplemented crn[8], opc1[4], crm[12], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
+warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6]
+warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
+warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1]
+warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: instruction 'mcr bpiall' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:27:42
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:21:54
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390
- 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390
+ 0: system.cpu0.isa: ISA system set to: 0x422cb00 0x422cb00
+ 0: system.cpu1.isa: ISA system set to: 0x422cb00 0x422cb00
---------- Begin Simulation Statistics ----------
-sim_seconds 2.539695 # Number of seconds simulated
-sim_ticks 2539695141000 # Number of ticks simulated
-final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.804329 # Number of seconds simulated
+sim_ticks 2804328920000 # Number of ticks simulated
+final_tick 2804328920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66572 # Simulator instruction rate (inst/s)
-host_op_rate 80202 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2802822069 # Simulator tick rate (ticks/s)
-host_mem_usage 418352 # Number of bytes of host memory used
-host_seconds 906.12 # Real time elapsed on the host
-sim_insts 60322278 # Number of instructions simulated
-sim_ops 72673006 # Number of ops (including micro ops) simulated
+host_inst_rate 115537 # Simulator instruction rate (inst/s)
+host_op_rate 140231 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2770199215 # Simulator tick rate (ticks/s)
+host_mem_usage 563788 # Number of bytes of host memory used
+host_seconds 1012.32 # Real time elapsed on the host
+sim_insts 116960928 # Number of instructions simulated
+sim_ops 141958852 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 4992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu0.inst 739456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5170528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 3968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4648772 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11204324 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 739456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1375040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6110656 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8446516 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 78 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293167 # Number of read requests accepted
-system.physmem.writeReqs 813006 # Number of write requests accepted
-system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 954783 # Per bank write bursts
-system.physmem.perBankRdBursts::1 950591 # Per bank write bursts
-system.physmem.perBankRdBursts::2 950729 # Per bank write bursts
-system.physmem.perBankRdBursts::3 950904 # Per bank write bursts
-system.physmem.perBankRdBursts::4 954888 # Per bank write bursts
-system.physmem.perBankRdBursts::5 951868 # Per bank write bursts
-system.physmem.perBankRdBursts::6 951800 # Per bank write bursts
-system.physmem.perBankRdBursts::7 951730 # Per bank write bursts
-system.physmem.perBankRdBursts::8 955391 # Per bank write bursts
-system.physmem.perBankRdBursts::9 951917 # Per bank write bursts
-system.physmem.perBankRdBursts::10 951458 # Per bank write bursts
-system.physmem.perBankRdBursts::11 951066 # Per bank write bursts
-system.physmem.perBankRdBursts::12 955340 # Per bank write bursts
-system.physmem.perBankRdBursts::13 951888 # Per bank write bursts
-system.physmem.perBankRdBursts::14 951979 # Per bank write bursts
-system.physmem.perBankRdBursts::15 951481 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6606 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6389 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6527 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6560 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6487 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6764 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6744 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6672 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7003 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6796 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6466 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6118 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7066 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6690 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6968 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6830 # Per bank write bursts
+system.physmem.num_reads::cpu0.inst 11554 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 81308 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 62 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 72638 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 175587 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 95479 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 136084 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 1780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 263684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1843767 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 226644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1657713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3995367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 263684 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 226644 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 490328 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2179008 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 826699 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3011956 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2179008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 827041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 1780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 263684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1850013 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 226644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1657716 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7007324 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 175588 # Number of read requests accepted
+system.physmem.writeReqs 136084 # Number of write requests accepted
+system.physmem.readBursts 175588 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 136084 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11230016 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8460224 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11204388 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8446516 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3871 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4656 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11119 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11133 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2539694027000 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 2804328669500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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-system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154323 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads
-system.physmem.totQLat 392436805250 # Total ticks spent queuing
-system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst
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+system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 64650 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 304.565754 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 178.964808 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 328.021120 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24334 37.64% 37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 15675 24.25% 61.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6689 10.35% 72.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3630 5.61% 77.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2748 4.25% 82.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1525 2.36% 84.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1125 1.74% 86.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1111 1.72% 87.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7813 12.09% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 64650 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.160877 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 477.303834 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.709408 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.238406 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.151792 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 6 0.09% 0.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 4 0.06% 0.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 11 0.16% 0.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5779 86.16% 86.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 101 1.51% 88.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 51 0.76% 88.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 232 3.46% 92.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 200 2.98% 95.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 21 0.31% 95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 22 0.33% 96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 12 0.18% 96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 28 0.42% 96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 8 0.12% 96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 5 0.07% 96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 157 2.34% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.07% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 5 0.07% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 11 0.16% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.03% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 5 0.07% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 4 0.06% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 4 0.06% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.10% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads
+system.physmem.totQLat 2725885000 # Total ticks spent queuing
+system.physmem.totMemAccLat 6015928750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 877345000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 15534.85 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 34284.85 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing
-system.physmem.readRowHits 14244486 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91200 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes
-system.physmem.avgGap 157684.51 # Average gap between requests
-system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states
-system.physmem.memoryStateTime::REF 84805760000 # Time in different power states
+system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 11.75 # Average write queue length when enqueuing
+system.physmem.readRowHits 145120 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97889 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes
+system.physmem.avgGap 8997692.03 # Average gap between requests
+system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2678489596250 # Time in different power states
+system.physmem.memoryStateTime::REF 93642640000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states
+system.physmem.memoryStateTime::ACT 32196672750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3810769200 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3815857080 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2079288750 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2082064875 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 59414885400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 59440056000 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 341813520 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 349511760 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 165880066560 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 165880066560 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 143884087110 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 144952782390 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1397598764250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1396661312250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1773009674790 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1773181650915 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.121024 # Core power per rank (mW)
-system.physmem.averagePower::1 698.188739 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16345693 # Transaction distribution
-system.membus.trans_dist::ReadResp 16345693 # Transaction distribution
-system.membus.trans_dist::WriteReq 763357 # Transaction distribution
-system.membus.trans_dist::WriteResp 763357 # Transaction distribution
-system.membus.trans_dist::Writeback 58988 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131549 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131549 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 217843 # Request fanout histogram
+system.physmem.actEnergy::0 258567120 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 230186880 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 141083250 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 125598000 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 715260000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 653390400 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 447145920 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 409451760 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 183165003840 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 183165003840 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 77778018765 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 76614000390 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1614369982500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1615391051250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1876875061395 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1876588682520 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.278202 # Core power per rank (mW)
+system.physmem.averagePower::1 669.176082 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 67981 # Transaction distribution
+system.membus.trans_dist::ReadResp 67980 # Transaction distribution
+system.membus.trans_dist::WriteReq 27608 # Transaction distribution
+system.membus.trans_dist::WriteResp 27608 # Transaction distribution
+system.membus.trans_dist::Writeback 95479 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 23 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4656 # Transaction distribution
+system.membus.trans_dist::ReadExReq 138435 # Transaction distribution
+system.membus.trans_dist::ReadExResp 138435 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464698 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 572340 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 645052 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17495585 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19814881 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 234 # Total snoops (count)
+system.membus.snoop_fanout::samples 310978 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 310978 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 217843 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 310978 # Request fanout histogram
+system.membus.reqLayer0.occupancy 81489000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1718500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1433405250 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1729661846 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38504711 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 64097 # number of replacements
-system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use
-system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks.
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.061035 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.061035 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68336.598557 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68765.495247 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 65472.600579 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.363985 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.188587 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.710795 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64453.987859 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65233.805214 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 64819.111498 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 33359 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 2655300 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2655214 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 703572 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2847 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 68 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296965 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296965 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3889644 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533488 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43405 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169876 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6636413 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124460352 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99828001 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 67144 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 295132 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 224650629 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 69040 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3663181 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.099289 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3626705 99.00% 99.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3663181 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4671577230 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 8759110629 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3910283961 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 26690343 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 96888385 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 30210 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30210 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7736387 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326614549 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36835289 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 26968745 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 14109241 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 549589 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 16704483 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 12571056 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 75.255583 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 6684107 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 29871 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 27184101 # DTB read hits
-system.cpu0.dtb.read_misses 37692 # DTB read misses
-system.cpu0.dtb.write_hits 5601213 # DTB write hits
-system.cpu0.dtb.write_misses 10069 # DTB write misses
-system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
+system.cpu0.dtb.read_hits 14281958 # DTB read hits
+system.cpu0.dtb.read_misses 49036 # DTB read misses
+system.cpu0.dtb.write_hits 10331652 # DTB write hits
+system.cpu0.dtb.write_misses 7432 # DTB write misses
+system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3418 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 971 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 27221793 # DTB read accesses
-system.cpu0.dtb.write_accesses 5611282 # DTB write accesses
+system.cpu0.dtb.perms_faults 583 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 14330994 # DTB read accesses
+system.cpu0.dtb.write_accesses 10339084 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 32785314 # DTB hits
-system.cpu0.dtb.misses 47761 # DTB misses
-system.cpu0.dtb.accesses 32833075 # DTB accesses
+system.cpu0.dtb.hits 24613610 # DTB hits
+system.cpu0.dtb.misses 56468 # DTB misses
+system.cpu0.dtb.accesses 24670078 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 5349776 # ITB inst hits
-system.cpu0.itb.inst_misses 7612 # ITB inst misses
+system.cpu0.itb.inst_hits 20359986 # ITB inst hits
+system.cpu0.itb.inst_misses 8688 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2307 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses
-system.cpu0.itb.hits 5349776 # DTB hits
-system.cpu0.itb.misses 7612 # DTB misses
-system.cpu0.itb.accesses 5357388 # DTB accesses
-system.cpu0.numCycles 234157878 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 20368674 # ITB inst accesses
+system.cpu0.itb.hits 20359986 # DTB hits
+system.cpu0.itb.misses 8688 # DTB misses
+system.cpu0.itb.accesses 20368674 # DTB accesses
+system.cpu0.numCycles 107845593 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 40386810 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 105587816 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 26968745 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 19255163 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 62197124 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3245751 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 127625 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 7153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 560512 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 142803 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 20358682 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 375797 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3540 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 105045556 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.208380 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.316447 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 76194887 72.54% 72.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 3754274 3.57% 76.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2490616 2.37% 78.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 7859227 7.48% 85.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1696652 1.62% 87.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 1110270 1.06% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 6030562 5.74% 94.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 1172073 1.12% 95.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4736995 4.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 105045556 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.250068 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.979065 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 27992831 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 58288752 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 15795686 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1494186 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1473806 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1905882 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 151125 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 87429633 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 488960 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1473806 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 28854522 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 7825241 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 44530433 # count of cycles rename stalled for serializing inst
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+system.cpu0.rename.UnblockCycles 5945509 # Number of cycles rename is unblocking
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+system.cpu0.rename.ROBFullEvents 2363 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 1232745 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 241627 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 3747183 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 86230749 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 384928079 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 93177414 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 5669 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 72449468 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13781265 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1547727 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1453455 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 8907873 # count of insts added to the skid buffer
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+system.cpu0.memDep0.insertedStores 11459129 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1951942 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2729865 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 80431590 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1054195 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 77118742 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 91388 # Number of squashed instructions issued
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+system.cpu0.iq.iqSquashedOperandsExamined 24751793 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 74311546 70.74% 70.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10189117 9.70% 80.44% # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::3 6570455 6.25% 94.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2322662 2.21% 96.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1491632 1.42% 97.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 1567348 1.49% 99.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 489722 0.47% 99.77% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::total 105045556 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 112665 9.94% 9.94% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 535473 47.24% 57.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 485278 42.82% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 2200 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 51451834 66.72% 66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 57694 0.07% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 4462 0.01% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 14684703 19.04% 85.84% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 10917839 14.16% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued
-system.cpu0.iq.rate 0.251847 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 77118742 # Type of FU issued
+system.cpu0.iq.rate 0.715085 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1133419 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 260495273 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 91574151 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 74667012 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12574 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5487 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 78243199 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6762 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 345945 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2206741 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2565 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 52530 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1128151 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 207860 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 209627 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1473806 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 5382891 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 2162428 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 81613092 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 131628 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 15026911 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 11459129 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 550936 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 43632 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2106388 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 52530 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 254626 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 219922 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 474548 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 76513772 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 14449148 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 548624 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 112477 # number of nop insts executed
-system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5651382 # Number of branches executed
-system.cpu0.iew.exec_stores 5868056 # Number of stores executed
-system.cpu0.iew.exec_rate 0.250110 # Inst execution rate
-system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 21614386 # num instructions producing a value
-system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value
+system.cpu0.iew.exec_nop 127307 # number of nop insts executed
+system.cpu0.iew.exec_refs 25261391 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 14437195 # Number of branches executed
+system.cpu0.iew.exec_stores 10812243 # Number of stores executed
+system.cpu0.iew.exec_rate 0.709475 # Inst execution rate
+system.cpu0.iew.wb_sent 75851893 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 74672499 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 39010696 # num instructions producing a value
+system.cpu0.iew.wb_consumers 67649101 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.692402 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.576662 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 11320580 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 939050 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 400483 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 102489063 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.685035 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.574738 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 75163014 73.34% 73.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 12241374 11.94% 85.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 6264234 6.11% 91.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2647997 2.58% 93.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1295474 1.26% 95.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 837997 0.82% 96.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1889450 1.84% 97.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 409985 0.40% 98.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1739538 1.70% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 29065490 # Number of instructions committed
-system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 102489063 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 57892234 # Number of instructions committed
+system.cpu0.commit.committedOps 70208613 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12095492 # Number of memory references committed
-system.cpu0.commit.loads 6522179 # Number of loads committed
-system.cpu0.commit.membars 193065 # Number of memory barriers committed
-system.cpu0.commit.branches 4958543 # Number of branches committed
-system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 472637 # Number of function calls committed.
+system.cpu0.commit.refs 23151148 # Number of memory references committed
+system.cpu0.commit.loads 12820170 # Number of loads committed
+system.cpu0.commit.membars 372459 # Number of memory barriers committed
+system.cpu0.commit.branches 13651808 # Number of branches committed
+system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 61466111 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 2656847 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 46997024 66.94% 66.94% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 55979 0.08% 67.02% # Class of committed instruction
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+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 4462 0.01% 67.03% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 12820170 18.26% 85.29% # Class of committed instruction
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system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 70208613 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1739538 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 270737391 # The number of ROB reads
-system.cpu0.rob.rob_writes 84952654 # The number of ROB writes
-system.cpu0.timesIdled 265059 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 28998871 # Number of Instructions Simulated
-system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads
-system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 292292897 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 986757 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.592826 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 987269 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 327.084830 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638838 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads 169616941 # The number of ROB reads
+system.cpu0.rob.rob_writes 165619058 # The number of ROB writes
+system.cpu0.timesIdled 398870 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 2800037 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2442123265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 57820351 # Number of Instructions Simulated
+system.cpu0.committedOps 70136730 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.865184 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.865184 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.536140 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.536140 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 83228446 # number of integer regfile reads
+system.cpu0.int_regfile_writes 47576245 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 16184 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 12998 # number of floating regfile writes
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+system.cpu0.cc_regfile_writes 28213628 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 191272649 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 720305 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 1943673 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.578352 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 38923517 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1944185 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 20.020480 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.782570 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.795782 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.536685 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.462492 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999176 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015931 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014671 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015290 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227248 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218800 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223107 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018132 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020805 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019558 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000098 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000191 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000148 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016103 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015596 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.015847 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018656 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017914 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13515.454235 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13659.203607 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.805822 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44222.700682 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42113.245985 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43193.446270 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15472.707600 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15419.061150 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15446.915145 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.451669 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15454.273884 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13826.948270 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14666.380952 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15616.659574 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15323.191176 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26433.549216 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25204.573814 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25822.802379 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24819.129525 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23841.006706 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24335.312868 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 8293404 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits
+system.cpu1.branchPred.lookups 27347291 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 14229080 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 552926 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 17264130 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 12844736 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 74.401293 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 6762355 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 29663 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 28281448 # DTB read hits
-system.cpu1.dtb.read_misses 40913 # DTB read misses
-system.cpu1.dtb.write_hits 6183126 # DTB write hits
-system.cpu1.dtb.write_misses 14267 # DTB write misses
-system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch
+system.cpu1.dtb.read_hits 14380313 # DTB read hits
+system.cpu1.dtb.read_misses 50338 # DTB read misses
+system.cpu1.dtb.write_hits 10697385 # DTB write hits
+system.cpu1.dtb.write_misses 9618 # DTB write misses
+system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 785 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 1275 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 28322361 # DTB read accesses
-system.cpu1.dtb.write_accesses 6197393 # DTB write accesses
+system.cpu1.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 14430651 # DTB read accesses
+system.cpu1.dtb.write_accesses 10707003 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 34464574 # DTB hits
-system.cpu1.dtb.misses 55180 # DTB misses
-system.cpu1.dtb.accesses 34519754 # DTB accesses
+system.cpu1.dtb.hits 25077698 # DTB hits
+system.cpu1.dtb.misses 59956 # DTB misses
+system.cpu1.dtb.accesses 25137654 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 5686404 # ITB inst hits
-system.cpu1.itb.inst_misses 8235 # ITB inst misses
+system.cpu1.itb.inst_hits 20651138 # ITB inst hits
+system.cpu1.itb.inst_misses 8123 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2271 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1349 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses
-system.cpu1.itb.hits 5686404 # DTB hits
-system.cpu1.itb.misses 8235 # DTB misses
-system.cpu1.itb.accesses 5694639 # DTB accesses
-system.cpu1.numCycles 237046957 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 20659261 # ITB inst accesses
+system.cpu1.itb.hits 20651138 # DTB hits
+system.cpu1.itb.misses 8123 # DTB misses
+system.cpu1.itb.accesses 20659261 # DTB accesses
+system.cpu1.numCycles 107249974 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 40725468 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 106761765 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 27347291 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 19607091 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 61565472 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3230729 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 119361 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 4162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 473 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 476136 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 133238 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 20649355 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 381272 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3428 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 104639861 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.227831 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.325701 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 75287195 71.95% 71.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 3919090 3.75% 75.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 2500009 2.39% 78.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 8110720 7.75% 85.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1591501 1.52% 87.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 1177075 1.12% 88.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 6154172 5.88% 94.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 1148436 1.10% 95.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4751663 4.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 104639861 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.254986 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.995448 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 27852312 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 57848791 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15754577 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1718968 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1464898 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1977106 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 152502 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 89215039 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 494329 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1464898 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 28797360 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 6699621 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 45356537 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 16519675 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 5801450 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 85333745 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 2191 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 1572004 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 242988 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 3188310 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 88168045 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 393456751 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 95320905 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6151 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 74288331 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13879714 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1591572 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1490290 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 10044487 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 15194391 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 11866887 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 2182296 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 2756146 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 82055126 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1162203 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 78681977 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 95018 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10109005 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 25435903 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 107068 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 104639861 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.751931 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.430939 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 72959997 69.72% 69.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 10709404 10.23% 79.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 8056823 7.70% 87.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 6679323 6.38% 94.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 2498342 2.39% 96.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1545149 1.48% 97.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1464114 1.40% 99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 496511 0.47% 99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 230198 0.22% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 104639861 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 103205 8.90% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 5 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 536017 46.20% 55.10% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 520896 44.90% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 137 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 52524607 66.76% 66.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 58923 0.07% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 4123 0.01% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 14785011 18.79% 85.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 11309172 14.37% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued
-system.cpu1.iq.rate 0.264594 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 78681977 # Type of FU issued
+system.cpu1.iq.rate 0.733632 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 1160123 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.014744 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 263245129 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 93371477 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 76291260 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 13827 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7286 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6040 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 79834510 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7453 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 367216 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2201674 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2649 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 53639 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1152377 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 193043 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 153958 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1464898 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 4313031 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 2150253 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 83357725 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 132748 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 15194391 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 11866887 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 585663 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 47230 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2090333 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 53639 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 255743 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 221088 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 476831 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 78071744 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 14543565 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 550444 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 134083 # number of nop insts executed
-system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6065757 # Number of branches executed
-system.cpu1.iew.exec_stores 6434518 # Number of stores executed
-system.cpu1.iew.exec_rate 0.262803 # Inst execution rate
-system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 23334628 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value
+system.cpu1.iew.exec_nop 140396 # number of nop insts executed
+system.cpu1.iew.exec_refs 25744293 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 14514927 # Number of branches executed
+system.cpu1.iew.exec_stores 11200728 # Number of stores executed
+system.cpu1.iew.exec_rate 0.727942 # Inst execution rate
+system.cpu1.iew.wb_sent 77444184 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 76297300 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 39931831 # num instructions producing a value
+system.cpu1.iew.wb_consumers 69996884 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.711397 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.570480 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 11439631 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 1055135 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 402423 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 102076918 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.704421 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.588048 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 73994277 72.49% 72.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 12594887 12.34% 84.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6447399 6.32% 91.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 2674121 2.62% 93.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1416644 1.39% 95.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 932745 0.91% 96.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1821915 1.78% 97.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 428135 0.42% 98.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1766795 1.73% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 31407169 # Number of instructions committed
-system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 102076918 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 59223599 # Number of instructions committed
+system.cpu1.commit.committedOps 71905144 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13153120 # Number of memory references committed
-system.cpu1.commit.loads 6992793 # Number of loads committed
-system.cpu1.commit.membars 210663 # Number of memory barriers committed
-system.cpu1.commit.branches 5351172 # Number of branches committed
-system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 519360 # Number of function calls committed.
+system.cpu1.commit.refs 23707227 # Number of memory references committed
+system.cpu1.commit.loads 12992717 # Number of loads committed
+system.cpu1.commit.membars 441930 # Number of memory barriers committed
+system.cpu1.commit.branches 13739507 # Number of branches committed
+system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 63021848 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 2684059 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 48136675 66.94% 66.94% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 57123 0.08% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 12992717 18.07% 85.10% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 10714510 14.90% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 71905144 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1766795 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 276729293 # The number of ROB reads
-system.cpu1.rob.rob_writes 91408516 # The number of ROB writes
-system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 31323407 # Number of Instructions Simulated
-system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads
-system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.cpu1.rob.rob_reads 171176371 # The number of ROB reads
+system.cpu1.rob.rob_writes 169257009 # The number of ROB writes
+system.cpu1.timesIdled 392905 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 2610113 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2951402872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 59140577 # Number of Instructions Simulated
+system.cpu1.committedOps 71822122 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.813475 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.813475 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.551427 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.551427 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 84961864 # number of integer regfile reads
+system.cpu1.int_regfile_writes 48575931 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 16615 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 13105 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 275730923 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 28983730 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 192710320 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 799493 # number of misc regfile writes
+system.iocache.tags.replacements 36423 # number of replacements
+system.iocache.tags.tagsinuse 0.982033 # Cycle average of tags in use
+system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 234020639000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.982033 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.061377 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.061377 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328241 # Number of tag accesses
+system.iocache.tags.data_accesses 328241 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
+system.iocache.demand_misses::total 249 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 249 # number of overall misses
+system.iocache.overall_misses::total 249 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 16710377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 16710377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2222587461 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2222587461 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 16710377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 16710377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 16710377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 19:11:44
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:26:21
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400
- 0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400
+ 0: system.cpu0.isa: ISA system set to: 0x3fa4b00 0x3fa4b00
+ 0: system.cpu1.isa: ISA system set to: 0x3fa4b00 0x3fa4b00
---------- Begin Simulation Statistics ----------
-sim_seconds 2.627904 # Number of seconds simulated
-sim_ticks 2627903712000 # Number of ticks simulated
-final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.904683 # Number of seconds simulated
+sim_ticks 2904682547500 # Number of ticks simulated
+final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 449186 # Simulator instruction rate (inst/s)
-host_op_rate 536465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19602826894 # Simulator tick rate (ticks/s)
-host_mem_usage 462988 # Number of bytes of host memory used
-host_seconds 134.06 # Real time elapsed on the host
-sim_insts 60216663 # Number of instructions simulated
-sim_ops 71917112 # Number of ops (including micro ops) simulated
+host_inst_rate 708228 # Simulator instruction rate (inst/s)
+host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18288406087 # Simulator tick rate (ticks/s)
+host_mem_usage 555560 # Number of bytes of host memory used
+host_seconds 158.83 # Real time elapsed on the host
+sim_insts 112485368 # Number of instructions simulated
+sim_ops 135622164 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory
-system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15690649 # Number of read requests accepted
-system.physmem.writeReqs 811422 # Number of write requests accepted
-system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 980414 # Per bank write bursts
-system.physmem.perBankRdBursts::1 980044 # Per bank write bursts
-system.physmem.perBankRdBursts::2 979984 # Per bank write bursts
-system.physmem.perBankRdBursts::3 980262 # Per bank write bursts
-system.physmem.perBankRdBursts::4 986671 # Per bank write bursts
-system.physmem.perBankRdBursts::5 980424 # Per bank write bursts
-system.physmem.perBankRdBursts::6 980555 # Per bank write bursts
-system.physmem.perBankRdBursts::7 980428 # Per bank write bursts
-system.physmem.perBankRdBursts::8 980781 # Per bank write bursts
-system.physmem.perBankRdBursts::9 980432 # Per bank write bursts
-system.physmem.perBankRdBursts::10 979731 # Per bank write bursts
-system.physmem.perBankRdBursts::11 979566 # Per bank write bursts
-system.physmem.perBankRdBursts::12 980337 # Per bank write bursts
-system.physmem.perBankRdBursts::13 980248 # Per bank write bursts
-system.physmem.perBankRdBursts::14 980396 # Per bank write bursts
-system.physmem.perBankRdBursts::15 980367 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6669 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6337 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6309 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6427 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6393 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6675 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6845 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6769 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7058 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6682 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6146 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6016 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6658 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6472 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6707 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6699 # Per bank write bursts
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 168816 # Number of read requests accepted
+system.physmem.writeReqs 123423 # Number of write requests accepted
+system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4512 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 9768 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9653 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10324 # Per bank write bursts
+system.physmem.perBankRdBursts::3 9994 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18675 # Per bank write bursts
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-system.physmem.totGap 2627899414000 # Total gap between requests
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-system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM
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+system.physmem.bytesPerActivate::384-511 3179 5.43% 76.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2288 3.91% 80.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1563 2.67% 83.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1023 1.75% 85.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1098 1.88% 86.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7614 13.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 58497 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads
+system.physmem.totQLat 1486718500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4649281000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8814.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27564.36 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.01 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing
-system.physmem.readRowHits 14667378 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87909 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes
-system.physmem.avgGap 159246.64 # Average gap between requests
-system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states
-system.physmem.memoryStateTime::REF 87751300000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing
+system.physmem.readRowHits 139009 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90713 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes
+system.physmem.avgGap 9939406.19 # Average gap between requests
+system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2756104323000 # Time in different power states
+system.physmem.memoryStateTime::REF 96993520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states
+system.physmem.memoryStateTime::ACT 51578552000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3933127800 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3930897600 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2146051875 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2144835000 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 61220499600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 61166492400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 339707520 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 339798240 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 171641542800 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 171641542800 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 154602145665 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 155429248725 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1441123214250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1440397685250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1835006289510 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1835050500015 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.278968 # Core power per rank (mW)
-system.physmem.averagePower::1 698.295792 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.physmem.actEnergy::0 224721000 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 217516320 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 122615625 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 118684500 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 86947680015 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 86005039095 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1666535934000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1667362812000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1944635925720 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1944428021475 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.484538 # Core power per rank (mW)
+system.physmem.averagePower::1 669.412962 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16743265 # Transaction distribution
-system.membus.trans_dist::ReadResp 16743265 # Transaction distribution
-system.membus.trans_dist::WriteReq 763389 # Transaction distribution
-system.membus.trans_dist::WriteResp 763389 # Transaction distribution
-system.membus.trans_dist::Writeback 57404 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131496 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131496 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 213883 # Request fanout histogram
+system.membus.trans_dist::ReadReq 70577 # Transaction distribution
+system.membus.trans_dist::ReadResp 70577 # Transaction distribution
+system.membus.trans_dist::WriteReq 27613 # Transaction distribution
+system.membus.trans_dist::WriteResp 27613 # Transaction distribution
+system.membus.trans_dist::Writeback 82818 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4510 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4512 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129059 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129059 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 545872 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 618569 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 15710305 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 18029601 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 219 # Total snoops (count)
+system.membus.snoop_fanout::samples 283020 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 283020 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 213883 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 283020 # Request fanout histogram
+system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1640330738 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 61855 # number of replacements
-system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use
-system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy
+system.l2c.tags.replacements 89435 # number of replacements
+system.l2c.tags.tagsinuse 64928.071050 # Cycle average of tags in use
+system.l2c.tags.total_refs 2766017 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 17.882651 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 50556.019026 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 2064.899937 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 5760.330467 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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-system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution
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-system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution
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-system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
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-system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution
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-system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes)
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-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 18167 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 2301461 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2301446 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415394 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5925128 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750524 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 205689601 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 53732 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.104795 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3246673 98.89% 98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4418861248 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 7658492249 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3782893262 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8184 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8184 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6554416 # DTB read hits
-system.cpu0.dtb.read_misses 6570 # DTB read misses
-system.cpu0.dtb.write_hits 5649486 # DTB write hits
-system.cpu0.dtb.write_misses 1771 # DTB write misses
-system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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-system.cpu0.dtb.read_accesses 6560986 # DTB read accesses
-system.cpu0.dtb.write_accesses 5651257 # DTB write accesses
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+system.cpu0.dtb.write_accesses 9835686 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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-system.cpu0.dtb.misses 8341 # DTB misses
-system.cpu0.dtb.accesses 12212243 # DTB accesses
+system.cpu0.dtb.hits 22124198 # DTB hits
+system.cpu0.dtb.misses 7024 # DTB misses
+system.cpu0.dtb.accesses 22131222 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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-system.cpu0.itb.inst_misses 3286 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
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-system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
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-system.cpu0.itb.misses 3286 # DTB misses
-system.cpu0.itb.accesses 30240354 # DTB accesses
-system.cpu0.numCycles 2626678485 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 58036248 # ITB inst accesses
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+system.cpu0.itb.accesses 58036248 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29654606 # Number of instructions committed
-system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses
-system.cpu0.num_func_calls 1084226 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 31825632 # number of integer instructions
-system.cpu0.num_fp_insts 5298 # number of float instructions
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-system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written
-system.cpu0.num_mem_refs 12632580 # number of memory refs
-system.cpu0.num_load_insts 6723962 # Number of load instructions
-system.cpu0.num_store_insts 5908618 # Number of store instructions
-system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles
-system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles
-system.cpu0.Branches 5094853 # Number of branches fetched
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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+system.cpu0.op_class::total 69618096 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 856352 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.726078 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45195.456335 # average WriteReq miss latency
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 686956 # number of writebacks
+system.cpu0.dcache.writebacks::total 686956 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7032 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7182 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14214 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 328 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 615 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205196 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 402199 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150195 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148466 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 298661 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57639 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59222 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 116861 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4095 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4463 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 347198 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 353662 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 700860 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 404837 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 412884 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 817721 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416554578 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121100447 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884346328 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 16236713697 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580384578 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 17674995947 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2687639750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5790667250 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4852954750 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220469750 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223161 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234332 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228686 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.481328 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.533886 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.501570 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.843160 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.664959 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.946843 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6613806 # DTB read hits
-system.cpu1.dtb.read_misses 7420 # DTB read misses
-system.cpu1.dtb.write_hits 5584575 # DTB write hits
-system.cpu1.dtb.write_misses 1868 # DTB write misses
-system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits 12236378 # DTB read hits
+system.cpu1.dtb.read_misses 5657 # DTB read misses
+system.cpu1.dtb.write_hits 9775690 # DTB write hits
+system.cpu1.dtb.write_misses 790 # DTB write misses
+system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6621226 # DTB read accesses
-system.cpu1.dtb.write_accesses 5586443 # DTB write accesses
+system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 12242035 # DTB read accesses
+system.cpu1.dtb.write_accesses 9776480 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 12198381 # DTB hits
-system.cpu1.dtb.misses 9288 # DTB misses
-system.cpu1.dtb.accesses 12207669 # DTB accesses
+system.cpu1.dtb.hits 22012068 # DTB hits
+system.cpu1.dtb.misses 6447 # DTB misses
+system.cpu1.dtb.accesses 22018515 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 31273770 # ITB inst hits
-system.cpu1.itb.inst_misses 4023 # ITB inst misses
+system.cpu1.itb.inst_hits 57551112 # ITB inst hits
+system.cpu1.itb.inst_misses 3277 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses
-system.cpu1.itb.hits 31273770 # DTB hits
-system.cpu1.itb.misses 4023 # DTB misses
-system.cpu1.itb.accesses 31277793 # DTB accesses
-system.cpu1.numCycles 2629128939 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 57554389 # ITB inst accesses
+system.cpu1.itb.hits 57551112 # DTB hits
+system.cpu1.itb.misses 3277 # DTB misses
+system.cpu1.itb.accesses 57554389 # DTB accesses
+system.cpu1.numCycles 2904045401 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30562057 # Number of instructions committed
-system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses
-system.cpu1.num_func_calls 1056400 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 32452923 # number of integer instructions
-system.cpu1.num_fp_insts 4971 # number of float instructions
-system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written
-system.cpu1.num_mem_refs 12626030 # number of memory refs
-system.cpu1.num_load_insts 6797131 # Number of load instructions
-system.cpu1.num_store_insts 5828899 # Number of store instructions
-system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles
-system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles
-system.cpu1.Branches 5215542 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction
-system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction
-system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction
-system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 55972216 # Number of instructions committed
+system.cpu1.committedOps 67554299 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 59752061 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses
+system.cpu1.num_func_calls 4972349 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 7584517 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 59752061 # number of integer instructions
+system.cpu1.num_fp_insts 5003 # number of float instructions
+system.cpu1.num_int_register_reads 108688873 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 41135339 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 244070995 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 25783519 # number of times the CC registers were written
+system.cpu1.num_mem_refs 22653694 # number of memory refs
+system.cpu1.num_load_insts 12397895 # Number of load instructions
+system.cpu1.num_store_insts 10255799 # Number of store instructions
+system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles
+system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles
+system.cpu1.Branches 12941354 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 46411426 67.14% 67.14% # Class of executed instruction
+system.cpu1.op_class::IntMult 56056 0.08% 67.22% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction
+system.cpu1.op_class::MemRead 12397895 17.94% 85.16% # Class of executed instruction
+system.cpu1.op_class::MemWrite 10255799 14.84% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 36855310 # Class of executed instruction
+system.cpu1.op_class::total 69125473 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36424 # number of replacements
+system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328122 # Number of tag accesses
+system.iocache.tags.data_accesses 328122 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
+system.iocache.demand_misses::total 234 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 234 # number of overall misses
+system.iocache.overall_misses::total 234 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
-warn: x86 cpuid: unimplemented function 8
-warn: x86 cpuid: unimplemented function 8
+warn: x86 cpuid: unknown family 0x8086
warn: Tried to clear PCI interrupt 14
warn: Unknown mouse command 0xe1.
warn: instruction 'wbinvd' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:13:07
-gem5 started Jun 21 2014 22:16:40
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Oct 29 2014 09:18:07
+gem5 started Oct 29 2014 09:27:02
+gem5 executing on u200540-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5137926173000 because m5_exit instruction encountered
+Exiting @ tick 5125902116500 because m5_exit instruction encountered
sim_ticks 5125902116500 # Number of ticks simulated
final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 254798 # Simulator instruction rate (inst/s)
-host_op_rate 503662 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3201100243 # Simulator tick rate (ticks/s)
-host_mem_usage 749084 # Number of bytes of host memory used
-host_seconds 1601.29 # Real time elapsed on the host
+host_inst_rate 196886 # Simulator instruction rate (inst/s)
+host_op_rate 389187 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2473535129 # Simulator tick rate (ticks/s)
+host_mem_usage 743248 # Number of bytes of host memory used
+host_seconds 2072.30 # Real time elapsed on the host
sim_insts 408006726 # Number of instructions simulated
sim_ops 806511598 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0xbacc
-warn: x86 cpuid: unknown family 0xbacc
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
-warn: x86 cpuid: unimplemented function 8
-warn: x86 cpuid: unimplemented function 8
warn: Tried to clear PCI interrupt 14
warn: Unknown mouse command 0xe1.
warn: instruction 'wbinvd' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:13:07
-gem5 started Jun 21 2014 22:18:32
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Oct 29 2014 09:18:07
+gem5 started Oct 29 2014 09:28:19
+gem5 executing on u200540-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
sim_ticks 5137751757500 # Number of ticks simulated
final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205879 # Simulator instruction rate (inst/s)
-host_op_rate 409313 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4343855741 # Simulator tick rate (ticks/s)
-host_mem_usage 976756 # Number of bytes of host memory used
-host_seconds 1182.76 # Real time elapsed on the host
+host_inst_rate 311526 # Simulator instruction rate (inst/s)
+host_op_rate 619354 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6572918502 # Simulator tick rate (ticks/s)
+host_mem_usage 927072 # Number of bytes of host memory used
+host_seconds 781.65 # Real time elapsed on the host
sim_insts 243506025 # Number of instructions simulated
sim_ops 484120527 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
sim_ticks 407883784500 # Number of ticks simulated
final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135225 # Simulator instruction rate (inst/s)
-host_op_rate 166480 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 86093843 # Simulator tick rate (ticks/s)
-host_mem_usage 2533572 # Number of bytes of host memory used
-host_seconds 4737.67 # Real time elapsed on the host
+host_inst_rate 91246 # Simulator instruction rate (inst/s)
+host_op_rate 112336 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58093586 # Simulator tick rate (ticks/s)
+host_mem_usage 2566152 # Number of bytes of host memory used
+host_seconds 7021.15 # Real time elapsed on the host
sim_insts 640649298 # Number of instructions simulated
sim_ops 788724957 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1200075862 # Number of instructions fetch has processed
+system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed
system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:25:12
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:02
gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 688618000
-Exiting @ tick 1960909874500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 690168000
+Exiting @ tick 1961826628500 because m5_exit instruction encountered
sim_ticks 1961826628500 # Number of ticks simulated
final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 855480 # Simulator instruction rate (inst/s)
-host_op_rate 855480 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27561784483 # Simulator tick rate (ticks/s)
-host_mem_usage 318220 # Number of bytes of host memory used
-host_seconds 71.18 # Real time elapsed on the host
+host_inst_rate 1248737 # Simulator instruction rate (inst/s)
+host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40231703865 # Simulator tick rate (ticks/s)
+host_mem_usage 312404 # Number of bytes of host memory used
+host_seconds 48.76 # Real time elapsed on the host
sim_insts 60892387 # Number of instructions simulated
sim_ops 60892387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:24:48
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:00
gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1920428041000 because m5_exit instruction encountered
+Exiting @ tick 1919439025000 because m5_exit instruction encountered
sim_ticks 1919439025000 # Number of ticks simulated
final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 960719 # Simulator instruction rate (inst/s)
-host_op_rate 960718 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32869301826 # Simulator tick rate (ticks/s)
-host_mem_usage 317196 # Number of bytes of host memory used
-host_seconds 58.40 # Real time elapsed on the host
+host_inst_rate 1406989 # Simulator instruction rate (inst/s)
+host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48137648137 # Simulator tick rate (ticks/s)
+host_mem_usage 309300 # Number of bytes of host memory used
+host_seconds 39.87 # Real time elapsed on the host
sim_insts 56102180 # Number of instructions simulated
sim_ops 56102180 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
latency=30000
latency_var=0
null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:07:33
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:03
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800
- 0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00
+ 0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 912096767500 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2802882496500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 0.900830 # Number of seconds simulated
-sim_ticks 900829868000 # Number of ticks simulated
-final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.802882 # Number of seconds simulated
+sim_ticks 2802882496500 # Number of ticks simulated
+final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1355321 # Simulator instruction rate (inst/s)
-host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19839612971 # Simulator tick rate (ticks/s)
-host_mem_usage 467260 # Number of bytes of host memory used
-host_seconds 45.41 # Real time elapsed on the host
-sim_insts 61539136 # Number of instructions simulated
-sim_ops 74139862 # Number of ops (including micro ops) simulated
+host_inst_rate 1330236 # Simulator instruction rate (inst/s)
+host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25395755903 # Simulator tick rate (ticks/s)
+host_mem_usage 564312 # Number of bytes of host memory used
+host_seconds 110.37 # Real time elapsed on the host
+sim_insts 146815698 # Number of instructions simulated
+sim_ops 178892459 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory
-system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 6129610 # Transaction distribution
-system.membus.trans_dist::ReadResp 6129610 # Transaction distribution
-system.membus.trans_dist::WriteReq 767040 # Transaction distribution
-system.membus.trans_dist::WriteResp 767040 # Transaction distribution
-system.membus.trans_dist::Writeback 52587 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution
-system.membus.trans_dist::ReadExReq 163617 # Transaction distribution
-system.membus.trans_dist::ReadExResp 136674 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes)
+system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 75963 # Transaction distribution
+system.membus.trans_dist::ReadResp 75963 # Transaction distribution
+system.membus.trans_dist::WriteReq 30903 # Transaction distribution
+system.membus.trans_dist::WriteResp 30903 # Transaction distribution
+system.membus.trans_dist::Writeback 95019 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution
+system.membus.trans_dist::ReadExReq 196321 # Transaction distribution
+system.membus.trans_dist::ReadExResp 152216 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses
+system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses
+system.l2c.overall_misses::cpu0.data 148112 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses
+system.l2c.overall_misses::cpu1.data 16956 # number of overall misses
+system.l2c.overall_misses::total 184307 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 52587 # number of writebacks
-system.l2c.writebacks::total 52587 # number of writebacks
+system.l2c.writebacks::writebacks 95019 # number of writebacks
+system.l2c.writebacks::total 95019 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 36713 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution
-system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7955 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7955 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
+system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7391828 # DTB read hits
-system.cpu0.dtb.read_misses 1916 # DTB read misses
-system.cpu0.dtb.write_hits 6659769 # DTB write hits
-system.cpu0.dtb.write_misses 1130 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits 20338466 # DTB read hits
+system.cpu0.dtb.read_misses 6871 # DTB read misses
+system.cpu0.dtb.write_hits 16389914 # DTB write hits
+system.cpu0.dtb.write_misses 1093 # DTB write misses
+system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7393744 # DTB read accesses
-system.cpu0.dtb.write_accesses 6660899 # DTB write accesses
+system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 20345337 # DTB read accesses
+system.cpu0.dtb.write_accesses 16391007 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14051597 # DTB hits
-system.cpu0.dtb.misses 3046 # DTB misses
-system.cpu0.dtb.accesses 14054643 # DTB accesses
+system.cpu0.dtb.hits 36728380 # DTB hits
+system.cpu0.dtb.misses 7964 # DTB misses
+system.cpu0.dtb.accesses 36736344 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 37936653 # ITB inst hits
-system.cpu0.itb.inst_misses 1207 # ITB inst misses
+system.cpu0.itb.inst_hits 97433991 # ITB inst hits
+system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses
-system.cpu0.itb.hits 37936653 # DTB hits
-system.cpu0.itb.misses 1207 # DTB misses
-system.cpu0.itb.accesses 37937860 # DTB accesses
-system.cpu0.numCycles 1801220958 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses
+system.cpu0.itb.hits 97433991 # DTB hits
+system.cpu0.itb.misses 3358 # DTB misses
+system.cpu0.itb.accesses 97437349 # DTB accesses
+system.cpu0.numCycles 5605766965 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 37699441 # Number of instructions committed
-system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses
-system.cpu0.num_func_calls 1205511 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39864660 # number of integer instructions
-system.cpu0.num_fp_insts 4171 # number of float instructions
-system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written
-system.cpu0.num_mem_refs 14597797 # number of memory refs
-system.cpu0.num_load_insts 7571468 # Number of load instructions
-system.cpu0.num_store_insts 7026329 # Number of store instructions
-system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles
-system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles
-system.cpu0.Branches 6054439 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction
-system.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 95421538 # Number of instructions committed
+system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
+system.cpu0.num_func_calls 7999979 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 100756647 # number of integer instructions
+system.cpu0.num_fp_insts 9755 # number of float instructions
+system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written
+system.cpu0.num_mem_refs 37871263 # number of memory refs
+system.cpu0.num_load_insts 20596038 # Number of load instructions
+system.cpu0.num_store_insts 17275225 # Number of store instructions
+system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles
+system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles
+system.cpu0.Branches 21940727 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction
+system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
+system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 45002955 # Class of executed instruction
+system.cpu0.op_class::total 116875407 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 346148 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements 1109428 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits
-system.cpu0.icache.overall_hits::total 37590948 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.750695 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.750695 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.033433 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057038 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.460109 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.271717 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.033433 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057038 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.460109 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.271717 # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks 114351 # number of writebacks
-system.cpu0.l2cache.writebacks::total 114351 # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks
+system.cpu0.l2cache.writebacks::total 192932 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 371621 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 458.751149 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 12812322 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 371931 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 34.448115 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses
-system.cpu0.dcache.overall_misses::total 405369 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses
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+system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses
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+system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total 769185 # number of overall misses
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+system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks
-system.cpu0.dcache.writebacks::total 323282 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks
+system.cpu0.dcache.writebacks::total 511188 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 229047 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 321922 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6029083 # DTB read hits
-system.cpu1.dtb.read_misses 5405 # DTB read misses
-system.cpu1.dtb.write_hits 4781968 # DTB write hits
-system.cpu1.dtb.write_misses 1104 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits 12172110 # DTB read hits
+system.cpu1.dtb.read_misses 2853 # DTB read misses
+system.cpu1.dtb.write_hits 7585805 # DTB write hits
+system.cpu1.dtb.write_misses 506 # DTB write misses
+system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6034488 # DTB read accesses
-system.cpu1.dtb.write_accesses 4783072 # DTB write accesses
+system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 12174963 # DTB read accesses
+system.cpu1.dtb.write_accesses 7586311 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 10811051 # DTB hits
-system.cpu1.dtb.misses 6509 # DTB misses
-system.cpu1.dtb.accesses 10817560 # DTB accesses
+system.cpu1.dtb.hits 19757915 # DTB hits
+system.cpu1.dtb.misses 3359 # DTB misses
+system.cpu1.dtb.accesses 19761274 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 24627232 # ITB inst hits
-system.cpu1.itb.inst_misses 3166 # ITB inst misses
+system.cpu1.itb.inst_hits 53664371 # ITB inst hits
+system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses
-system.cpu1.itb.hits 24627232 # DTB hits
-system.cpu1.itb.misses 3166 # DTB misses
-system.cpu1.itb.accesses 24630398 # DTB accesses
-system.cpu1.numCycles 1801708036 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses
+system.cpu1.itb.hits 53664371 # DTB hits
+system.cpu1.itb.misses 1734 # DTB misses
+system.cpu1.itb.accesses 53666105 # DTB accesses
+system.cpu1.numCycles 5605295863 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 23839695 # Number of instructions committed
-system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses
-system.cpu1.num_func_calls 987959 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 25548618 # number of integer instructions
-system.cpu1.num_fp_insts 5779 # number of float instructions
-system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written
-system.cpu1.num_mem_refs 11166773 # number of memory refs
-system.cpu1.num_load_insts 6206724 # Number of load instructions
-system.cpu1.num_store_insts 4960049 # Number of store instructions
-system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles
-system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles
-system.cpu1.Branches 4459767 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction
-system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction
-system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 51394160 # Number of instructions committed
+system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
+system.cpu1.num_func_calls 9170283 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 56976202 # number of integer instructions
+system.cpu1.num_fp_insts 1792 # number of float instructions
+system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written
+system.cpu1.num_mem_refs 20022980 # number of memory refs
+system.cpu1.num_load_insts 12287666 # Number of load instructions
+system.cpu1.num_store_insts 7735314 # Number of store instructions
+system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles
+system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles
+system.cpu1.Branches 15216192 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction
+system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
+system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 29271769 # Class of executed instruction
+system.cpu1.op_class::total 65450545 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements 398154 # number of replacements
-system.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements 523179 # number of replacements
+system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 49656500 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 49656500 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 24230251 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 24230251 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 24230251 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 24230251 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 24230251 # number of overall hits
-system.cpu1.icache.overall_hits::total 24230251 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 398666 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 398666 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 398666 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 398666 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 398666 # number of overall misses
-system.cpu1.icache.overall_misses::total 398666 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 24628917 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 24628917 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 24628917 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 24628917 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 24628917 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 24628917 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016187 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016187 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.016187 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016187 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits
+system.cpu1.icache.overall_hits::total 53141770 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses
+system.cpu1.icache.overall_misses::total 523691 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements 88565 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks.
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits
-system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses
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-system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses
-system.cpu1.dcache.overall_misses::total 327250 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses
+system.cpu1.dcache.tags.replacements 191901 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy
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+system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits
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+system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits
+system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses
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+system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 259772 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks
-system.cpu1.dcache.writebacks::total 209707 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks
+system.cpu1.dcache.writebacks::total 120669 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 259574 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes)
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+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes)
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+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 499577 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram
+system.iocache.tags.replacements 36442 # number of replacements
+system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328284 # Number of tag accesses
+system.iocache.tags.data_accesses 328284 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
+system.iocache.demand_misses::total 252 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 252 # number of overall misses
+system.iocache.overall_misses::total 252 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
latency=30000
latency_var=0
null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:06:34
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:56:38
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.isa: ISA system set to: 0x55f5800 0x55f5800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2332810269000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2783853461500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.321335 # Number of seconds simulated
-sim_ticks 2321335404000 # Number of ticks simulated
-final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.783853 # Number of seconds simulated
+sim_ticks 2783853461500 # Number of ticks simulated
+final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1308981 # Simulator instruction rate (inst/s)
-host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50301976363 # Simulator tick rate (ticks/s)
-host_mem_usage 455960 # Number of bytes of host memory used
-host_seconds 46.15 # Real time elapsed on the host
-sim_insts 60406834 # Number of instructions simulated
-sim_ops 72742429 # Number of ops (including micro ops) simulated
+host_inst_rate 1369296 # Simulator instruction rate (inst/s)
+host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26699855189 # Simulator tick rate (ticks/s)
+host_mem_usage 553552 # Number of bytes of host memory used
+host_seconds 104.26 # Real time elapsed on the host
+sim_insts 142769281 # Number of instructions simulated
+sim_ops 173798567 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 14973631 # Transaction distribution
-system.membus.trans_dist::ReadResp 14973631 # Transaction distribution
-system.membus.trans_dist::WriteReq 763122 # Transaction distribution
-system.membus.trans_dist::WriteResp 763122 # Transaction distribution
-system.membus.trans_dist::Writeback 57873 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131874 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131874 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 74236 # Transaction distribution
+system.membus.trans_dist::ReadResp 74236 # Transaction distribution
+system.membus.trans_dist::WriteReq 27560 # Transaction distribution
+system.membus.trans_dist::WriteResp 27560 # Transaction distribution
+system.membus.trans_dist::Writeback 101898 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214751 # Request fanout histogram
+system.membus.snoop_fanout::samples 322857 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 214751 # Request fanout histogram
+system.membus.snoop_fanout::total 322857 # Request fanout histogram
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution
-system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8131 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8131 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13142243 # DTB read hits
-system.cpu.dtb.read_misses 7297 # DTB read misses
-system.cpu.dtb.write_hits 11216207 # DTB write hits
-system.cpu.dtb.write_misses 2181 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB
+system.cpu.dtb.read_hits 31525428 # DTB read hits
+system.cpu.dtb.read_misses 8580 # DTB read misses
+system.cpu.dtb.write_hits 23123837 # DTB write hits
+system.cpu.dtb.write_misses 1448 # DTB write misses
+system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 13149540 # DTB read accesses
-system.cpu.dtb.write_accesses 11218388 # DTB write accesses
+system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 31534008 # DTB read accesses
+system.cpu.dtb.write_accesses 23125285 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 24358450 # DTB hits
-system.cpu.dtb.misses 9478 # DTB misses
-system.cpu.dtb.accesses 24367928 # DTB accesses
+system.cpu.dtb.hits 54649265 # DTB hits
+system.cpu.dtb.misses 10028 # DTB misses
+system.cpu.dtb.accesses 54659293 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 61430007 # ITB inst hits
-system.cpu.itb.inst_misses 4471 # ITB inst misses
+system.cpu.itb.inst_hits 147035651 # ITB inst hits
+system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61434478 # ITB inst accesses
-system.cpu.itb.hits 61430007 # DTB hits
-system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61434478 # DTB accesses
-system.cpu.numCycles 4642753590 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 147040413 # ITB inst accesses
+system.cpu.itb.hits 147035651 # DTB hits
+system.cpu.itb.misses 4762 # DTB misses
+system.cpu.itb.accesses 147040413 # DTB accesses
+system.cpu.numCycles 5567710004 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60406834 # Number of instructions committed
-system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2135762 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls
-system.cpu.num_int_insts 64191430 # number of integer instructions
-system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read
-system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written
-system.cpu.num_mem_refs 25221274 # number of memory refs
-system.cpu.num_load_insts 13499937 # Number of load instructions
-system.cpu.num_store_insts 11721337 # Number of store instructions
-system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles
-system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles
-system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.984109 # Percentage of idle cycles
-system.cpu.Branches 10298517 # Number of branches fetched
-system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
-system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram
+system.iocache.tags.replacements 36430 # number of replacements
+system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328176 # Number of tag accesses
+system.iocache.tags.data_accesses 328176 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
+system.iocache.demand_misses::total 240 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 240 # number of overall misses
+system.iocache.overall_misses::total 240 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:08:43
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:33
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu0.isa: ISA system set to: 0x6319800 0x6319800
- 0: system.cpu1.isa: ISA system set to: 0x6319800 0x6319800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu0.isa: ISA system set to: 0x5550b00 0x5550b00
+ 0: system.cpu1.isa: ISA system set to: 0x5550b00 0x5550b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1196139241000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2866929256000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.675181 # Number of seconds simulated
-sim_ticks 2675180779000 # Number of ticks simulated
-final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.866929 # Number of seconds simulated
+sim_ticks 2866929256000 # Number of ticks simulated
+final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 349036 # Simulator instruction rate (inst/s)
-host_op_rate 416751 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14917331050 # Simulator tick rate (ticks/s)
-host_mem_usage 433588 # Number of bytes of host memory used
-host_seconds 179.33 # Real time elapsed on the host
-sim_insts 62593972 # Number of instructions simulated
-sim_ops 74737529 # Number of ops (including micro ops) simulated
+host_inst_rate 703930 # Simulator instruction rate (inst/s)
+host_op_rate 851474 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15295798763 # Simulator tick rate (ticks/s)
+host_mem_usage 599572 # Number of bytes of host memory used
+host_seconds 187.43 # Real time elapsed on the host
+sim_insts 131939289 # Number of instructions simulated
+sim_ops 159593891 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory
-system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2675178052500 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads
-system.physmem.totQLat 408788863752 # Total ticks spent queuing
-system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
+system.physmem.totQLat 5972474500 # Total ticks spent queuing
+system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.96 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.06 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing
-system.physmem.readRowHits 14689438 # Number of row buffer hits during reads
-system.physmem.writeRowHits 84116 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes
-system.physmem.avgGap 161771.61 # Average gap between requests
-system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states
-system.physmem.memoryStateTime::REF 89330020000 # Time in different power states
+system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
+system.physmem.readRowHits 175001 # Number of row buffer hits during reads
+system.physmem.writeRowHits 85560 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes
+system.physmem.avgGap 8293327.90 # Average gap between requests
+system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states
+system.physmem.memoryStateTime::REF 95733040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states
+system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3975289920 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3974851440 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2169057000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2168817750 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 61291097400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 61250069400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 371874240 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 371731680 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 174729519120 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 174729519120 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 149034867885 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 147923300340 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1474373657250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1475348716500 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1865945362815 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1865767006230 # Total energy per rank (pJ)
-system.physmem.averagePower::0 697.503604 # Core power per rank (mW)
-system.physmem.averagePower::1 697.436933 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16891737 # Transaction distribution
-system.membus.trans_dist::ReadResp 16891737 # Transaction distribution
-system.membus.trans_dist::WriteReq 769090 # Transaction distribution
-system.membus.trans_dist::WriteResp 769090 # Transaction distribution
-system.membus.trans_dist::Writeback 67188 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 15580 # Transaction distribution
-system.membus.trans_dist::ReadExResp 8709 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 70292 # Total snoops (count)
-system.membus.snoop_fanout::samples 326383 # Request fanout histogram
+system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ)
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+system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.477790 # Core power per rank (mW)
+system.physmem.averagePower::1 669.355049 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 228441 # Transaction distribution
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+system.membus.trans_dist::WriteResp 31177 # Transaction distribution
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+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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+system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
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+system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 129081 # Total snoops (count)
+system.membus.snoop_fanout::samples 475718 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 326383 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 475718 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 91391 # number of replacements
-system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use
-system.l2c.tags.total_refs 364235 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks.
+system.l2c.tags.replacements 132728 # number of replacements
+system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use
+system.l2c.tags.total_refs 489645 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor
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+system.l2c.overall_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.413428 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 171942 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 305065 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8087 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8087 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59408 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7131006 # DTB read hits
-system.cpu0.dtb.read_misses 3644 # DTB read misses
-system.cpu0.dtb.write_hits 6127729 # DTB write hits
-system.cpu0.dtb.write_misses 663 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits 24353899 # DTB read hits
+system.cpu0.dtb.read_misses 6408 # DTB read misses
+system.cpu0.dtb.write_hits 18126722 # DTB write hits
+system.cpu0.dtb.write_misses 1115 # DTB write misses
+system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7134650 # DTB read accesses
-system.cpu0.dtb.write_accesses 6128392 # DTB write accesses
+system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24360307 # DTB read accesses
+system.cpu0.dtb.write_accesses 18127837 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 13258735 # DTB hits
-system.cpu0.dtb.misses 4307 # DTB misses
-system.cpu0.dtb.accesses 13263042 # DTB accesses
+system.cpu0.dtb.hits 42480621 # DTB hits
+system.cpu0.dtb.misses 7523 # DTB misses
+system.cpu0.dtb.accesses 42488144 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 31182741 # ITB inst hits
-system.cpu0.itb.inst_misses 2176 # ITB inst misses
+system.cpu0.itb.inst_hits 115074724 # ITB inst hits
+system.cpu0.itb.inst_misses 3350 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses
-system.cpu0.itb.hits 31182741 # DTB hits
-system.cpu0.itb.misses 2176 # DTB misses
-system.cpu0.itb.accesses 31184917 # DTB accesses
-system.cpu0.numCycles 5349463018 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses
+system.cpu0.itb.hits 115074724 # DTB hits
+system.cpu0.itb.misses 3350 # DTB misses
+system.cpu0.itb.accesses 115078074 # DTB accesses
+system.cpu0.numCycles 5733858512 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 30507218 # Number of instructions committed
-system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
-system.cpu0.num_func_calls 1290775 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 32859018 # number of integer instructions
-system.cpu0.num_fp_insts 5449 # number of float instructions
-system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13795466 # number of memory refs
-system.cpu0.num_load_insts 7343231 # Number of load instructions
-system.cpu0.num_store_insts 6452235 # Number of store instructions
-system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles
-system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles
-system.cpu0.Branches 5660514 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction
-system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction
-system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 111430460 # Number of instructions committed
+system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
+system.cpu0.num_func_calls 12527987 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls
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system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.766332 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.766332 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.925498 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.925498 # mshr miss rate for SCUpgradeReq accesses
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system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149554 # mshr miss rate for ReadExReq accesses
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+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses
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+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133 # average ReadReq mshr miss latency
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-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825 # average HardPFReq mshr miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466 # average SCUpgradeReq mshr miss latency
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-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 444000 # average SCUpgradeFailReq mshr miss latency
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-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782 # average ReadExReq mshr miss latency
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-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 355829 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970640 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.970640 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 330 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 330 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.644531 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 24668842 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 24668842 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5548461 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5548461 # number of ReadReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 62661 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 153118 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 153118 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152372 # number of StoreCondReq hits
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-system.cpu0.dcache.demand_hits::cpu0.data 11320350 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 11383011 # number of overall hits
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-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 66756 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 66756 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10498 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 10498 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11173 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 11173 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 362225 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 362225 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 428981 # number of overall misses
-system.cpu0.dcache.overall_misses::total 428981 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2139066005 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 2139066005 # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 2832298001 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 176126000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 176126000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 261398841 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 261398841 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1128000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1128000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 4971364006 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 4971364006 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 286365 # number of writebacks
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.writebacks::total 483937 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 631972 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 991588 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6599972 # DTB read hits
-system.cpu1.dtb.read_misses 3720 # DTB read misses
-system.cpu1.dtb.write_hits 5539858 # DTB write hits
-system.cpu1.dtb.write_misses 1581 # DTB write misses
-system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits 4827395 # DTB read hits
+system.cpu1.dtb.read_misses 2744 # DTB read misses
+system.cpu1.dtb.write_hits 4131070 # DTB write hits
+system.cpu1.dtb.write_misses 524 # DTB write misses
+system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6603692 # DTB read accesses
-system.cpu1.dtb.write_accesses 5541439 # DTB write accesses
+system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 4830139 # DTB read accesses
+system.cpu1.dtb.write_accesses 4131594 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 12139830 # DTB hits
-system.cpu1.dtb.misses 5301 # DTB misses
-system.cpu1.dtb.accesses 12145131 # DTB accesses
+system.cpu1.dtb.hits 8958465 # DTB hits
+system.cpu1.dtb.misses 3268 # DTB misses
+system.cpu1.dtb.accesses 8961733 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 32728613 # ITB inst hits
-system.cpu1.itb.inst_misses 2200 # ITB inst misses
+system.cpu1.itb.inst_hits 20889672 # ITB inst hits
+system.cpu1.itb.inst_misses 1747 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses
-system.cpu1.itb.hits 32728613 # DTB hits
-system.cpu1.itb.misses 2200 # DTB misses
-system.cpu1.itb.accesses 32730813 # DTB accesses
-system.cpu1.numCycles 5350361558 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses
+system.cpu1.itb.hits 20889672 # DTB hits
+system.cpu1.itb.misses 1747 # DTB misses
+system.cpu1.itb.accesses 20891419 # DTB accesses
+system.cpu1.numCycles 5732950771 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32086754 # Number of instructions committed
-system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
-system.cpu1.num_func_calls 973285 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 33961237 # number of integer instructions
-system.cpu1.num_fp_insts 4436 # number of float instructions
-system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written
-system.cpu1.num_mem_refs 12531559 # number of memory refs
-system.cpu1.num_load_insts 6744563 # Number of load instructions
-system.cpu1.num_store_insts 5786996 # Number of store instructions
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-system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency
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-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 313601 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 19290 # number of SoftPFReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 75753 # number of StoreCondReq hits
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-system.cpu1.dcache.overall_hits::total 10761460 # number of overall hits
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-system.cpu1.dcache.SoftPFReq_misses::total 43327 # number of SoftPFReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 13673 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 365507 # number of overall misses
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 524000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 6370663 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency
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+system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks.
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+system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks
-system.cpu1.dcache.writebacks::total 225255 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses
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-system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks
+system.cpu1.dcache.writebacks::total 134926 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 549743 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 818131 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36443 # number of replacements
+system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328549 # Number of tag accesses
+system.iocache.tags.data_accesses 328549 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 253 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses
+system.iocache.demand_misses::total 253 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 253 # number of overall misses
+system.iocache.overall_misses::total 253 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
min_writes_per_switch=16
null=false
page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:08:28
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:15
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.isa: ISA system set to: 0x6b2c800 0x6b2c800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x56b5b00 0x56b5b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2616536483000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2902619131000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.614572 # Number of seconds simulated
-sim_ticks 2614571564500 # Number of ticks simulated
-final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.902619 # Number of seconds simulated
+sim_ticks 2902619131000 # Number of ticks simulated
+final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 393660 # Simulator instruction rate (inst/s)
-host_op_rate 470163 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17100811132 # Simulator tick rate (ticks/s)
-host_mem_usage 408168 # Number of bytes of host memory used
-host_seconds 152.89 # Real time elapsed on the host
-sim_insts 60187274 # Number of instructions simulated
-sim_ops 71883961 # Number of ops (including micro ops) simulated
+host_inst_rate 744858 # Simulator instruction rate (inst/s)
+host_op_rate 898074 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19216925045 # Simulator tick rate (ticks/s)
+host_mem_usage 553548 # Number of bytes of host memory used
+host_seconds 151.05 # Real time elapsed on the host
+sim_insts 112506996 # Number of instructions simulated
+sim_ops 135649573 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15495012 # Number of read requests accepted
-system.physmem.writeReqs 812156 # Number of write requests accepted
-system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 968097 # Per bank write bursts
-system.physmem.perBankRdBursts::1 967810 # Per bank write bursts
-system.physmem.perBankRdBursts::2 967673 # Per bank write bursts
-system.physmem.perBankRdBursts::3 967915 # Per bank write bursts
-system.physmem.perBankRdBursts::4 974446 # Per bank write bursts
-system.physmem.perBankRdBursts::5 968066 # Per bank write bursts
-system.physmem.perBankRdBursts::6 967653 # Per bank write bursts
-system.physmem.perBankRdBursts::7 967482 # Per bank write bursts
-system.physmem.perBankRdBursts::8 968460 # Per bank write bursts
-system.physmem.perBankRdBursts::9 968209 # Per bank write bursts
-system.physmem.perBankRdBursts::10 967967 # Per bank write bursts
-system.physmem.perBankRdBursts::11 967960 # Per bank write bursts
-system.physmem.perBankRdBursts::12 967930 # Per bank write bursts
-system.physmem.perBankRdBursts::13 967880 # Per bank write bursts
-system.physmem.perBankRdBursts::14 967953 # Per bank write bursts
-system.physmem.perBankRdBursts::15 967685 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6670 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6386 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6320 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6360 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6634 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6864 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6659 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6574 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7028 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6769 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6571 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6645 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6565 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6383 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6560 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6462 # Per bank write bursts
+system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 168277 # Number of read requests accepted
+system.physmem.writeReqs 122785 # Number of write requests accepted
+system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 9709 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9253 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2614567301000 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
+system.physmem.totGap 2902618699500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads
-system.physmem.totQLat 400730693500 # Total ticks spent queuing
-system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst
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+system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads
+system.physmem.totQLat 1491787750 # Total ticks spent queuing
+system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.98 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing
-system.physmem.readRowHits 14482679 # Number of row buffer hits during reads
-system.physmem.writeRowHits 88673 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes
-system.physmem.avgGap 160332.39 # Average gap between requests
-system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states
-system.physmem.memoryStateTime::REF 87306180000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing
+system.physmem.readRowHits 138438 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90000 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes
+system.physmem.avgGap 9972509.98 # Average gap between requests
+system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states
+system.physmem.memoryStateTime::REF 96924620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states
+system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3884796720 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3881470320 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 2119680750 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 2117865750 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 60443307600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 60403543200 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 339986160 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 343329840 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 170770888080 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 170770888080 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 155970246555 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 156681731385 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1431925089750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1431300980250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1825453995615 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1825499808825 # Total energy per rank (pJ)
-system.physmem.averagePower::0 698.185571 # Core power per rank (mW)
-system.physmem.averagePower::1 698.203093 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.480430 # Core power per rank (mW)
+system.physmem.averagePower::1 669.392372 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16546657 # Transaction distribution
-system.membus.trans_dist::ReadResp 16546657 # Transaction distribution
-system.membus.trans_dist::WriteReq 763381 # Transaction distribution
-system.membus.trans_dist::WriteResp 763381 # Transaction distribution
-system.membus.trans_dist::Writeback 58138 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
-system.membus.trans_dist::ReadExReq 132459 # Transaction distribution
-system.membus.trans_dist::ReadExResp 132459 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 215583 # Request fanout histogram
+system.membus.trans_dist::ReadReq 70650 # Transaction distribution
+system.membus.trans_dist::ReadResp 70650 # Transaction distribution
+system.membus.trans_dist::WriteReq 27618 # Transaction distribution
+system.membus.trans_dist::WriteResp 27618 # Transaction distribution
+system.membus.trans_dist::Writeback 82180 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
+system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
+system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 219 # Total snoops (count)
+system.membus.snoop_fanout::samples 281834 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 215583 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 281834 # Request fanout histogram
+system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8182 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8182 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13160242 # DTB read hits
-system.cpu.dtb.read_misses 7329 # DTB read misses
-system.cpu.dtb.write_hits 11228050 # DTB write hits
-system.cpu.dtb.write_misses 2212 # DTB write misses
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB
+system.cpu.dtb.read_hits 24532668 # DTB read hits
+system.cpu.dtb.read_misses 8148 # DTB read misses
+system.cpu.dtb.write_hits 19614514 # DTB write hits
+system.cpu.dtb.write_misses 1410 # DTB write misses
+system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 13167571 # DTB read accesses
-system.cpu.dtb.write_accesses 11230262 # DTB write accesses
+system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24540816 # DTB read accesses
+system.cpu.dtb.write_accesses 19615924 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 24388292 # DTB hits
-system.cpu.dtb.misses 9541 # DTB misses
-system.cpu.dtb.accesses 24397833 # DTB accesses
+system.cpu.dtb.hits 44147182 # DTB hits
+system.cpu.dtb.misses 9558 # DTB misses
+system.cpu.dtb.accesses 44156740 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 61481095 # ITB inst hits
-system.cpu.itb.inst_misses 4471 # ITB inst misses
+system.cpu.itb.inst_hits 115605897 # ITB inst hits
+system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61485566 # ITB inst accesses
-system.cpu.itb.hits 61481095 # DTB hits
-system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61485566 # DTB accesses
-system.cpu.numCycles 5229143129 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 115610659 # ITB inst accesses
+system.cpu.itb.hits 115605897 # DTB hits
+system.cpu.itb.misses 4762 # DTB misses
+system.cpu.itb.accesses 115610659 # DTB accesses
+system.cpu.numCycles 5805238262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60187274 # Number of instructions committed
-system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139801 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls
-system.cpu.num_int_insts 64248492 # number of integer instructions
-system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read
-system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written
-system.cpu.num_mem_refs 25244235 # number of memory refs
-system.cpu.num_load_insts 13512788 # Number of load instructions
-system.cpu.num_store_insts 11731447 # Number of store instructions
-system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles
-system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles
-system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.876666 # Percentage of idle cycles
-system.cpu.Branches 10306630 # Number of branches fetched
-system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction
-system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
-system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction
-system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction
+system.cpu.committedInsts 112506996 # Number of instructions committed
+system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed
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+system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 90404594 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 11249411 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 9965441 # number of WriteReq hits
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-system.cpu.dcache.SoftPFReq_hits::total 84252 # number of SoftPFReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 236461 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 247668 # number of StoreCondReq hits
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-system.cpu.dcache.ReadReq_misses::total 294699 # number of ReadReq misses
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-system.cpu.dcache.SoftPFReq_misses::total 100108 # number of SoftPFReq misses
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-system.cpu.dcache.LoadLockedReq_misses::total 11208 # number of LoadLockedReq misses
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-system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 595027 # number of writebacks
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency
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+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 18590 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 52963 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36424 # number of replacements
+system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328122 # Number of tag accesses
+system.iocache.tags.data_accesses 328122 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
+system.iocache.demand_misses::total 234 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 234 # number of overall misses
+system.iocache.overall_misses::total 234 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu0.istage2_mmu]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu1.istage2_mmu]
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
-use_default_range=false
+use_default_range=true
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
eventq_index=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
[system.iocache.tags]
type=LRU
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c.tags]
type=LRU
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
latency=30000
latency_var=0
null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
pio_latency=100000
system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
[system.realview.cf_ctrl]
type=IdeController
-BAR0=402653184
+BAR0=471465984
BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
-disks=system.cf0
+disks=
eventq_index=0
-io_shift=1
+io_shift=2
pci_bus=2
-pci_dev=7
+pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
[system.realview.clcd]
type=Pl111
enable_capture=true
eventq_index=0
gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
pio_latency=10000
pixel_clock=41667
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
pio_latency=100000
system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
pio=system.iobus.master[25]
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
int_latency=10000
system=system
pio=system.membus.master[2]
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
clk_domain=system.clk_domain
+enable_capture=true
eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
[system.realview.kmi0]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=52
+int_num=44
is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
[system.realview.kmi1]
type=Pl050
eventq_index=0
gic=system.realview.gic
int_delay=1000000
-int_num=53
+int_num=45
is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
pio_latency=100000
pio_size=4095
ret_bad_addr=false
system=system
update_data=false
warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
pio_latency=100000
system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
[system.realview.mmc_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
pio_latency=100000
system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
latency=30000
latency_var=0
null=false
-range=2147483648:2214592511
+range=0:67108863
port=system.membus.master[1]
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
system=system
pio=system.iobus.master[1]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
[system.realview.sp810_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
pio_latency=100000
system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
[system.realview.timer0]
type=Sp804
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
clock1=1000000
eventq_index=0
gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
eventq_index=0
gic=system.realview.gic
int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
pio_latency=100000
platform=system.realview
system=system
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
pio_latency=100000
system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
[system.realview.uart2_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
pio_latency=100000
system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
[system.realview.uart3_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
pio_latency=100000
system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
[system.realview.watchdog_fake]
type=AmbaFake
clk_domain=system.clk_domain
eventq_index=0
ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
pio_latency=100000
system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
[system.terminal]
type=Terminal
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:10:38
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:00:04
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x56d2400 0x56d2400
- 0: system.cpu1.isa: ISA system set to: 0x56d2400 0x56d2400
+ 0: system.cpu0.isa: ISA system set to: 0x50c1b00 0x50c1b00
+ 0: system.cpu1.isa: ISA system set to: 0x50c1b00 0x50c1b00
---------- Begin Simulation Statistics ----------
-sim_seconds 2.321335 # Number of seconds simulated
-sim_ticks 2321335404000 # Number of ticks simulated
-final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.783853 # Number of seconds simulated
+sim_ticks 2783853461500 # Number of ticks simulated
+final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1185543 # Simulator instruction rate (inst/s)
-host_op_rate 1427641 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45558461303 # Simulator tick rate (ticks/s)
-host_mem_usage 457752 # Number of bytes of host memory used
-host_seconds 50.95 # Real time elapsed on the host
-sim_insts 60406834 # Number of instructions simulated
-sim_ops 72742429 # Number of ops (including micro ops) simulated
+host_inst_rate 1402368 # Simulator instruction rate (inst/s)
+host_op_rate 1707157 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27344724772 # Simulator tick rate (ticks/s)
+host_mem_usage 555568 # Number of bytes of host memory used
+host_seconds 101.81 # Real time elapsed on the host
+sim_insts 142769281 # Number of instructions simulated
+sim_ops 173798567 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 508104 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5777624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 197312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 3294400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 508104 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 197312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1461532 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1554284 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14151 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 90301 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3083 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 51475 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 365383 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 388571 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 218884 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2488923 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 84999 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1419183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 218884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 84999 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1595551 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 629608 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 669565 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2894723 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1595551 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 218884 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3118531 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 84999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2088748 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54536653 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 727076 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4668128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 483904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5677444 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 727076 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 483904 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6521088 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8856948 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 19814 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73458 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 7561 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 88711 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 101892 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142497 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 261176 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1676858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 173825 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2039419 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4151808 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 261176 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 173825 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2342468 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3181542 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2342468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 261176 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1683150 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 173825 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2039422 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7333350 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 14973628 # Transaction distribution
-system.membus.trans_dist::ReadResp 14973628 # Transaction distribution
-system.membus.trans_dist::WriteReq 763122 # Transaction distribution
-system.membus.trans_dist::WriteResp 763122 # Transaction distribution
-system.membus.trans_dist::Writeback 57872 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4519 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4519 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131877 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131877 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4279044 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31804164 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16497384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18894255 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 128994735 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 74230 # Transaction distribution
+system.membus.trans_dist::ReadResp 74230 # Transaction distribution
+system.membus.trans_dist::WriteReq 27560 # Transaction distribution
+system.membus.trans_dist::WriteResp 27560 # Transaction distribution
+system.membus.trans_dist::Writeback 101892 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 606180 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679108 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18258695 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20592391 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214752 # Request fanout histogram
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+system.l2c.ReadReq_accesses::cpu0.inst 844186 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 256522 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 4990 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 855309 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 264503 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 682262 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 682262 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 136275 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 162630 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 844186 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 392797 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 4990 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 855309 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 427133 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2533851 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 844186 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 392797 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 4990 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 855309 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 427133 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2533851 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.012790 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.038012 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.008840 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.469389 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.515883 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.012790 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.187672 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.008840 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.209949 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.012790 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.187672 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.008840 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.209949 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 57872 # number of writebacks
-system.l2c.writebacks::total 57872 # number of writebacks
+system.l2c.writebacks::writebacks 101892 # number of writebacks
+system.l2c.writebacks::total 101892 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2455233 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2455233 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 592674 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 247191 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 247191 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1715294 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5740366 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22916 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51076 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7529652 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83268947 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45832 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102152 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 137908479 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 2107457 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 2291806 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2291806 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 682262 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417070 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444902 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20772 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41576 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5924320 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323083 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41544 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83152 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 205252639 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 36632 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3272100 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 2107457 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3235636 98.89% 98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 2107457 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution
-system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8131 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8131 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3272100 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6816435 # DTB read hits
-system.cpu0.dtb.read_misses 6211 # DTB read misses
-system.cpu0.dtb.write_hits 6254825 # DTB write hits
-system.cpu0.dtb.write_misses 2049 # DTB write misses
-system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5541 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits 15997245 # DTB read hits
+system.cpu0.dtb.read_misses 4798 # DTB read misses
+system.cpu0.dtb.write_hits 11281299 # DTB write hits
+system.cpu0.dtb.write_misses 897 # DTB write misses
+system.cpu0.dtb.flush_tlb 2812 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 3224 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 120 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 779 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6822646 # DTB read accesses
-system.cpu0.dtb.write_accesses 6256874 # DTB write accesses
+system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 16002043 # DTB read accesses
+system.cpu0.dtb.write_accesses 11282196 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 13071260 # DTB hits
-system.cpu0.dtb.misses 8260 # DTB misses
-system.cpu0.dtb.accesses 13079520 # DTB accesses
+system.cpu0.dtb.hits 27278544 # DTB hits
+system.cpu0.dtb.misses 5695 # DTB misses
+system.cpu0.dtb.accesses 27284239 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 32152502 # ITB inst hits
-system.cpu0.itb.inst_misses 3598 # ITB inst misses
+system.cpu0.itb.inst_hits 74797989 # ITB inst hits
+system.cpu0.itb.inst_misses 2590 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb 2812 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1905 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 32156100 # ITB inst accesses
-system.cpu0.itb.hits 32152502 # DTB hits
-system.cpu0.itb.misses 3598 # DTB misses
-system.cpu0.itb.accesses 32156100 # DTB accesses
-system.cpu0.numCycles 4610022066 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 74800579 # ITB inst accesses
+system.cpu0.itb.hits 74797989 # DTB hits
+system.cpu0.itb.misses 2590 # DTB misses
+system.cpu0.itb.accesses 74800579 # DTB accesses
+system.cpu0.numCycles 5536445370 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 31655881 # Number of instructions committed
-system.cpu0.committedOps 38589756 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 34002307 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5498 # Number of float alu accesses
-system.cpu0.num_func_calls 1192858 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4013764 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 34002307 # number of integer instructions
-system.cpu0.num_fp_insts 5498 # number of float instructions
-system.cpu0.num_int_register_reads 62271464 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22558612 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3941 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 115497170 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 15275707 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13519126 # number of memory refs
-system.cpu0.num_load_insts 6992673 # Number of load instructions
-system.cpu0.num_store_insts 6526453 # Number of store instructions
-system.cpu0.num_idle_cycles 4538759726.926458 # Number of idle cycles
-system.cpu0.num_busy_cycles 71262339.073542 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.015458 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.984542 # Percentage of idle cycles
-system.cpu0.Branches 5545179 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 16079 0.04% 0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu 25081623 64.87% 64.91% # Class of executed instruction
-system.cpu0.op_class::IntMult 45922 0.12% 65.03% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 1365 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.03% # Class of executed instruction
-system.cpu0.op_class::MemRead 6992673 18.09% 83.12% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6526453 16.88% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 72639024 # Number of instructions committed
+system.cpu0.committedOps 87981151 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 77491342 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses
+system.cpu0.num_func_calls 8694279 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 9459647 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 77491342 # number of integer instructions
+system.cpu0.num_fp_insts 5273 # number of float instructions
+system.cpu0.num_int_register_reads 144069707 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 54447285 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 268877072 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 31833969 # number of times the CC registers were written
+system.cpu0.num_mem_refs 27909499 # number of memory refs
+system.cpu0.num_load_insts 16164843 # Number of load instructions
+system.cpu0.num_store_insts 11744656 # Number of store instructions
+system.cpu0.num_idle_cycles 5353619097.982533 # Number of idle cycles
+system.cpu0.num_busy_cycles 182826272.017466 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles
+system.cpu0.Branches 18600717 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 61776214 68.83% 68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult 59687 0.07% 68.90% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::MemRead 16164843 18.01% 86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite 11744656 13.09% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 38664115 # Class of executed instruction
+system.cpu0.op_class::total 89752000 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 850504 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 60581751 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.338382 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.351248 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871755 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127639 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements 1698994 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 145339246 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.122338 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.541342 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888911 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110432 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 62283783 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 62283783 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 31695864 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 28885887 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 60581751 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 31695864 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 28885887 # number of demand (read+write) hits
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+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227093 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019461 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017522 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012626 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.013129 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014543 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 592674 # number of writebacks
-system.cpu0.dcache.writebacks::total 592674 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 682262 # number of writebacks
+system.cpu0.dcache.writebacks::total 682262 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6322311 # DTB read hits
-system.cpu1.dtb.read_misses 4545 # DTB read misses
-system.cpu1.dtb.write_hits 4960387 # DTB write hits
-system.cpu1.dtb.write_misses 1127 # DTB write misses
-system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3056 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits 15526476 # DTB read hits
+system.cpu1.dtb.read_misses 5406 # DTB read misses
+system.cpu1.dtb.write_hits 11842298 # DTB write hits
+system.cpu1.dtb.write_misses 791 # DTB write misses
+system.cpu1.dtb.flush_tlb 2818 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 3194 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6326856 # DTB read accesses
-system.cpu1.dtb.write_accesses 4961514 # DTB write accesses
+system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 15531882 # DTB read accesses
+system.cpu1.dtb.write_accesses 11843089 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 11282698 # DTB hits
-system.cpu1.dtb.misses 5672 # DTB misses
-system.cpu1.dtb.accesses 11288370 # DTB accesses
+system.cpu1.dtb.hits 27368774 # DTB hits
+system.cpu1.dtb.misses 6197 # DTB misses
+system.cpu1.dtb.accesses 27374971 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 29275767 # ITB inst hits
-system.cpu1.itb.inst_misses 2611 # ITB inst misses
+system.cpu1.itb.inst_hits 72236782 # ITB inst hits
+system.cpu1.itb.inst_misses 3052 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1680 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb 2818 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2023 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 29278378 # ITB inst accesses
-system.cpu1.itb.hits 29275767 # DTB hits
-system.cpu1.itb.misses 2611 # DTB misses
-system.cpu1.itb.accesses 29278378 # DTB accesses
-system.cpu1.numCycles 143033518 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 72239834 # ITB inst accesses
+system.cpu1.itb.hits 72236782 # DTB hits
+system.cpu1.itb.misses 3052 # DTB misses
+system.cpu1.itb.accesses 72239834 # DTB accesses
+system.cpu1.numCycles 88012648 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 28750953 # Number of instructions committed
-system.cpu1.committedOps 34152673 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 30189123 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4771 # Number of float alu accesses
-system.cpu1.num_func_calls 942904 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3531220 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 30189123 # number of integer instructions
-system.cpu1.num_fp_insts 4771 # number of float instructions
-system.cpu1.num_int_register_reads 54155883 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 20259495 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3552 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 102072834 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 13702034 # number of times the CC registers were written
-system.cpu1.num_mem_refs 11702148 # number of memory refs
-system.cpu1.num_load_insts 6507264 # Number of load instructions
-system.cpu1.num_store_insts 5194884 # Number of store instructions
-system.cpu1.num_idle_cycles 140979209.208319 # Number of idle cycles
-system.cpu1.num_busy_cycles 2054308.791681 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.014362 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.985638 # Percentage of idle cycles
-system.cpu1.Branches 4753338 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 12439 0.04% 0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 22454409 65.63% 65.67% # Class of executed instruction
-system.cpu1.op_class::IntMult 41849 0.12% 65.79% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 748 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.79% # Class of executed instruction
-system.cpu1.op_class::MemRead 6507264 19.02% 84.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite 5194884 15.18% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 70130257 # Number of instructions committed
+system.cpu1.committedOps 85817416 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 75667160 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses
+system.cpu1.num_func_calls 8179026 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 9270368 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 75667160 # number of integer instructions
+system.cpu1.num_fp_insts 6211 # number of float instructions
+system.cpu1.num_int_register_reads 140982352 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 52729123 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 261962982 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 30529174 # number of times the CC registers were written
+system.cpu1.num_mem_refs 28028313 # number of memory refs
+system.cpu1.num_load_insts 15690218 # Number of load instructions
+system.cpu1.num_store_insts 12338095 # Number of store instructions
+system.cpu1.num_idle_cycles 85358107.940046 # Number of idle cycles
+system.cpu1.num_busy_cycles 2654540.059954 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles
+system.cpu1.Branches 17795350 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 59373450 67.88% 67.88% # Class of executed instruction
+system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction
+system.cpu1.op_class::MemRead 15690218 17.94% 85.89% # Class of executed instruction
+system.cpu1.op_class::MemWrite 12338095 14.11% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 34211593 # Class of executed instruction
+system.cpu1.op_class::total 87463263 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.replacements 36430 # number of replacements
+system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses 0 # Number of tag accesses
-system.iocache.tags.data_accesses 0 # Number of data accesses
+system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 328176 # Number of tag accesses
+system.iocache.tags.data_accesses 328176 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
+system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
+system.iocache.demand_misses::total 240 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 240 # number of overall misses
+system.iocache.overall_misses::total 240 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 17:30:19
+gem5 compiled Oct 29 2014 09:18:07
+gem5 started Oct 29 2014 09:26:24
gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5196390180000 because m5_exit instruction encountered
+Exiting @ tick 5194410635000 because m5_exit instruction encountered
sim_ticks 5194410635000 # Number of ticks simulated
final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 693425 # Simulator instruction rate (inst/s)
-host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28047460404 # Simulator tick rate (ticks/s)
-host_mem_usage 637768 # Number of bytes of host memory used
-host_seconds 185.20 # Real time elapsed on the host
+host_inst_rate 1079720 # Simulator instruction rate (inst/s)
+host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43672253601 # Simulator tick rate (ticks/s)
+host_mem_usage 589096 # Number of bytes of host memory used
+host_seconds 118.94 # Real time elapsed on the host
sim_insts 128422722 # Number of instructions simulated
sim_ops 247557000 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses
system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
projects / gem5.git / commitdiff