projects / yosys.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 229e545)
Compute sigP properly
authorEddie Hung <eddie@fpgeh.com>
Wed, 4 Sep 2019 23:59:57 +0000 (16:59 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 4 Sep 2019 23:59:57 +0000 (16:59 -0700)
passes/pmgen/xilinx_dsp.pmg patch | blob | history

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 9b01c22ee95001d3562697ef4d7c9b05669ee53b..c45e92d6f885e90b9e447d8bb5608e424ed2d63a 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -189,7 +189,7 @@ code ffP sigP clock
 
                clock = c;
 
-               sigP = port(ffP, \Q);
+               sigP.replace(port(ffP, \D), port(ffP, \Q));
        }
 endcode