soc: add shadow_address parameter

When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 4ea520dd7307efcce6a92ef0670eaef7a38853fd..354339f39a0940ee59bbc024e3636d70035485bd 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -29,16 +29,17 @@ class SoC(Module):
         "timer0": 1,
     }
     mem_map = {
-        "rom":      0x00000000,  # (shadow @0x80000000)
-        "sram":     0x10000000,  # (shadow @0x90000000)
-        "main_ram": 0x40000000,  # (shadow @0xc0000000)
-        "csr":      0x60000000,  # (shadow @0xe0000000)
+        "rom":      0x00000000,  # (default shadow @0x80000000)
+        "sram":     0x10000000,  # (default shadow @0x90000000)
+        "main_ram": 0x40000000,  # (default shadow @0xc0000000)
+        "csr":      0x60000000,  # (default shadow @0xe0000000)
     }
     def __init__(self, platform, clk_freq,
                 cpu_type="lm32", cpu_reset_address=0x00000000,
                 integrated_rom_size=0,
                 integrated_sram_size=4096,
                 integrated_main_ram_size=0,
+                shadow_address=0x80000000,
                 with_csr=True, csr_data_width=8, csr_address_width=14,
                 with_uart=True, uart_baudrate=115200,
                 with_identifier=True,
@@ -60,6 +61,8 @@ class SoC(Module):
 
         self.with_identifier = with_identifier
 
+        self.shadow_address = shadow_address
+
         self.with_csr = with_csr
         self.csr_data_width = csr_data_width
         self.csr_address_width = csr_address_width
@@ -190,9 +193,9 @@ class SoC(Module):
                 data_width=self.csr_data_width, address_width=self.csr_address_width)
             self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
             for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-                self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
+                self.add_csr_region(name, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, csrs)
             for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-                self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)
+                self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, memory)
 
         # Interrupts
         if hasattr(self.cpu_or_bridge, "interrupt"):

diff --git a/targets/kc705.py b/targets/kc705.py
index cda3d8e18c9d41c746e9f14c63b9aa2c10be54fa..cdffafdae969d3750bc1db3d5a74b2d8783dc0c0 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -125,6 +125,6 @@ class MiniSoC(BaseSoC):
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
 
 default_subtarget = BaseSoC

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 378c8d0416e36d8a89446e179782a9451d5fe0d5..b05caae64de0f17f950f86f87dbbda40a680164c 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -101,7 +101,7 @@ class MiniSoC(BaseSoC):
                                             platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
 
 
 def get_vga_dvi(platform):

diff --git a/targets/simple.py b/targets/simple.py
index de7f21e8e8b9091f732124c0eabc8446090bd377..095ab910a85ae6f2185ba94e78873e0f3febf949 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -43,6 +43,6 @@ class MiniSoC(BaseSoC):
                                             interface="wishbone",
                                             with_hw_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
 
 default_subtarget = BaseSoC