(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index c69cce01da10b62e8904f9a70424e2a9e3f4e94b..415588659447118cb38b36a711d8ced60056a4d4 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -5,6 +5,8 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
 * [[svp64]]
 * [[sv/branches]]
+* [[opnpower/isa/sprset]]
+* [[/openpower/isa/condition]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element