libmesa_i965_gen75 \
libmesa_i965_gen8 \
libmesa_i965_gen9 \
- libmesa_i965_gen10
+ libmesa_i965_gen10 \
+ libmesa_i965_gen11
# ---------------------------------------
# Build libmesa_i965_gen4
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
+# ---------------------------------------
+# Build libmesa_i965_gen11
+# ---------------------------------------
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_i965_gen11
+
+LOCAL_C_INCLUDES := $(I965_PERGEN_COMMON_INCLUDES)
+
+LOCAL_SRC_FILES := $(i965_gen11_FILES)
+
+LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
+
+LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=110
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
# ---------------------------------------
# Build i965_dri
# ---------------------------------------
libi965_gen75.la \
libi965_gen8.la \
libi965_gen9.la \
- libi965_gen10.la
+ libi965_gen10.la \
+ libi965_gen11.la
libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
libi965_gen10_la_SOURCES = $(i965_gen10_FILES)
libi965_gen10_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=100
+libi965_gen11_la_SOURCES = $(i965_gen11_FILES)
+libi965_gen11_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=110
+
noinst_LTLIBRARIES = \
libi965_dri.la \
$(I965_PERGEN_LIBS)
genX_blorp_exec.c \
genX_state_upload.c
+i965_gen11_FILES = \
+ genX_blorp_exec.c \
+ genX_state_upload.c
+
i965_oa_GENERATED_FILES = \
brw_oa_hsw.h \
brw_oa_hsw.c \
case 10:
brw->blorp.exec = gen10_blorp_exec;
break;
+ case 11:
+ brw->blorp.exec = gen11_blorp_exec;
+ break;
+
default:
unreachable("Invalid gen");
}
const struct blorp_params *params);
void gen10_blorp_exec(struct blorp_batch *batch,
const struct blorp_params *params);
+void gen11_blorp_exec(struct blorp_batch *batch,
+ const struct blorp_params *params);
#ifdef __cplusplus
} /* extern "C" */
void gen8_init_atoms(struct brw_context *brw);
void gen9_init_atoms(struct brw_context *brw);
void gen10_init_atoms(struct brw_context *brw);
+void gen11_init_atoms(struct brw_context *brw);
/* Memory Object Control State:
* Specifying zero for L3 means "uncached in L3", at least on Haswell
brw_init_caches(brw);
- if (devinfo->gen >= 10)
+ if (devinfo->gen >= 11)
+ gen11_init_atoms(brw);
+ else if (devinfo->gen >= 10)
gen10_init_atoms(brw);
else if (devinfo->gen >= 9)
gen9_init_atoms(brw);
)
i965_gen_libs = []
-foreach v : ['40', '45', '50', '60', '70', '75', '80', '90', '100']
+foreach v : ['40', '45', '50', '60', '70', '75', '80', '90', '100', '110']
i965_gen_libs += static_library(
'libi965_gen@0@'.format(v),
['genX_blorp_exec.c', 'genX_state_upload.c', gen_xml_pack],