projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
d8f6d7b
)
Import module attributes from Verific
author
Miodrag Milanovic
<mmicko@gmail.com>
Sun, 10 Oct 2021 08:01:45 +0000
(10:01 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Sun, 10 Oct 2021 08:01:45 +0000
(10:01 +0200)
frontends/verific/verific.cc
patch
|
blob
|
history
diff --git
a/frontends/verific/verific.cc
b/frontends/verific/verific.cc
index 23100375396efe5dd12dccd60df07b3c7996a960..c03e16eb2264ee8bd5c04de27b3351e942e55649 100644
(file)
--- a/
frontends/verific/verific.cc
+++ b/
frontends/verific/verific.cc
@@
-917,6
+917,7
@@
void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
+ import_attributes(module->attributes, nl, nl);
SetIter si;
MapIter mi, mi2;