For "mulxu", store unsigned product in ACC.

Test.

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index d801cb2d4f55183cd76cbfaf212622a145bbc0b4..b1a9568510a8f9e564780d35779ab5bd5dea6e5e 100644 (file)
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -2,6 +2,7 @@ Tue Dec  2 15:01:08 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * simops.c (OP_3A00): For "macu", perform multiply stage using 32
        bit rather than 16 bit precision.
+       (OP_3C00): For "mulxu", store unsigned product in ACC.
 
 Tue Dec  2 11:04:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 

diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 6f12e5a69b1456f78f1ba2cec6fd2e2b43949e1a..e5a0825b91b6fef1f121af376c143026650ff8cc 100644 (file)
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1577,11 +1577,14 @@ OP_1C00 ()
 void
 OP_3C00 ()
 {
-  int64 tmp;
+  uint64 tmp;
+  uint32 src1;
+  uint32 src2;
 
   trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
-  tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
-
+  src1 = (uint16) State.regs[OP[1]];
+  src2 = (uint16) State.regs[OP[2]];
+  tmp = src1 * src2;
   if (State.FX)
     tmp <<= 1;
 

diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index c93cba1e7f64adde123f14b088faa9d524d089e3..f5b7cc61f770a6aeca286e35c989a963e3bb7f9d 100644 (file)
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -13,6 +13,7 @@ t-macros.i
 t-mac.s
 t-rachi.s
 t-rep.s
+t-mulxu.s
 t-subi.s
 t-sub2w.s
 t-mvtac.s

diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index 773737c56b6a342626429846ed74fcbebdeb83ca..fc34fc1e5106a23b866f30436da76679be931693 100644 (file)
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,6 +1,7 @@
 Tue Dec  2 11:01:36 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
-       * t-sub2w.s: New file.
+       * t-sub2w.s, t-mulxu.s, t-mac.s t-mvtac.s : New files.
+       
        * Makefile.in: Update.
 
 Mon Nov 17 20:14:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index d7fc13093c873a55afccf8eca0079bdc6bde786b..d358327cc393478675cfc2c41d3f76bbb1876324 100644 (file)
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -40,12 +40,14 @@ RPATH_ENVVAR = @RPATH_ENVVAR@
 TESTS = \
        exit47.ko \
        hello.hi \
+       t-mac.ok \
+       t-mvtac.ok \
+       t-mulxu.ok \
        t-rachi.ok \
        t-rep.ok \
-       t-subi.ok \
        t-sub2w.ok \
-       t-mvtac.ok \
-       t-mac.ok 
+       t-subi.ok \
+#
 
 AS_FOR_TARGET = `\
   if [ -x ../../../gas/as-new ]; then \

diff --git a/sim/testsuite/d10v-elf/t-mulxu.s b/sim/testsuite/d10v-elf/t-mulxu.s
new file mode 100644 (file)
index 0000000..a8e6ffc
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-mulxu.s
@@ -0,0 +1,28 @@
+.include "t-macros.i"
+
+       start
+
+       ;; clear FX
+       ldi r2, #0x8005
+       mvtc r2, cr0
+
+       loadacc2 a1 0x7f 0xffff 0xffff
+       ldi r8, 0xffff
+       ldi r9, 0x8001
+test_mulxu1:
+       MULXU a1, r9, r8
+       checkacc2 1 a1 0x00 0x8000 0x7FFF
+
+       
+       ;; set FX
+       ldi r2, #0x8085
+       mvtc r2, cr0
+
+       loadacc2 a1 0x7f 0xffff 0xffff
+       ldi r8, 0xffff
+       ldi r9, 0x8001
+test_mulxu2:
+       MULXU a1, r9, r8
+       checkacc2 2 a1 0x01 0x0000 0xFFFE
+
+       exit0