y1 = fabs(vp->scale[1]) * -1.0f + vp->translate[1];
y2 = fabs(vp->scale[1]) * 1.0f + vp->translate[1];
enable_guardband =
- (x1 <= 0.0f && x2 >= (float) ilo->framebuffer.width &&
- y1 <= 0.0f && y2 >= (float) ilo->framebuffer.height);
+ (x1 <= 0.0f && x2 >= (float) ilo->fb.state.width &&
+ y1 <= 0.0f && y2 >= (float) ilo->fb.state.height);
p->gen6_3DSTATE_CLIP(p->dev,
&ilo->rasterizer->state,
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
- ilo->framebuffer.width, ilo->framebuffer.height, p->cp);
+ ilo->fb.state.width, ilo->fb.state.height, p->cp);
}
}
const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
const int num_samplers =
ilo->samplers[PIPE_SHADER_FRAGMENT].num_samplers;
- const bool dual_blend = (!ilo->blend->logicop_enable &&
- ilo->blend->rt[0].blend_enable &&
- util_blend_state_is_dual(ilo->blend, 0));
- const bool cc_may_kill = (ilo->depth_stencil_alpha->alpha.enabled ||
- ilo->blend->alpha_to_coverage);
+ const bool dual_blend =
+ (!ilo->blend->state.logicop_enable &&
+ ilo->blend->state.rt[0].blend_enable &&
+ util_blend_state_is_dual(&ilo->blend->state, 0));
+ const bool cc_may_kill = (ilo->dsa->state.alpha.enabled ||
+ ilo->blend->state.alpha_to_coverage);
if (fs)
assert(!fs->pcb.clip_state_size);
/* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
const uint32_t *packed_sample_pos;
- int num_samples = 1;
- if (ilo->framebuffer.nr_cbufs)
- num_samples = ilo->framebuffer.cbufs[0]->texture->nr_samples;
-
- packed_sample_pos = (num_samples > 1) ?
+ packed_sample_pos = (ilo->fb.num_samples > 1) ?
&p->packed_sample_position_4x : &p->packed_sample_position_1x;
if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_wm_multisample_flush(p);
}
- p->gen6_3DSTATE_MULTISAMPLE(p->dev, num_samples, packed_sample_pos,
+ p->gen6_3DSTATE_MULTISAMPLE(p->dev,
+ ilo->fb.num_samples, packed_sample_pos,
ilo->rasterizer->state.half_pixel_center, p->cp);
p->gen6_3DSTATE_SAMPLE_MASK(p->dev,
- (num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
+ (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
}
}
}
p->gen6_3DSTATE_DEPTH_BUFFER(p->dev,
- ilo->framebuffer.zsbuf, false, p->cp);
+ ilo->fb.state.zsbuf, false, p->cp);
/* TODO */
p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
/* BLEND_STATE */
if (DIRTY(BLEND) || DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA)) {
p->state.BLEND_STATE = p->gen6_BLEND_STATE(p->dev,
- ilo->blend, &ilo->framebuffer,
- &ilo->depth_stencil_alpha->alpha, p->cp);
+ &ilo->blend->state, &ilo->fb, &ilo->dsa->state.alpha, p->cp);
session->cc_state_blend_changed = true;
}
/* COLOR_CALC_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
- p->state.COLOR_CALC_STATE = p->gen6_COLOR_CALC_STATE(p->dev,
- &ilo->stencil_ref,
- ilo->depth_stencil_alpha->alpha.ref_value,
- &ilo->blend_color, p->cp);
+ p->state.COLOR_CALC_STATE =
+ p->gen6_COLOR_CALC_STATE(p->dev, &ilo->stencil_ref,
+ ilo->dsa->state.alpha.ref_value, &ilo->blend_color, p->cp);
session->cc_state_cc_changed = true;
}
/* DEPTH_STENCIL_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA)) {
p->state.DEPTH_STENCIL_STATE =
- p->gen6_DEPTH_STENCIL_STATE(p->dev,
- ilo->depth_stencil_alpha, p->cp);
+ p->gen6_DEPTH_STENCIL_STATE(p->dev, &ilo->dsa->state, p->cp);
session->cc_state_dsa_changed = true;
}
uint32_t *surface_state = &p->state.wm.SURFACE_STATE[offset];
int i;
- for (i = 0; i < ilo->framebuffer.nr_cbufs; i++) {
- const struct pipe_surface *surface = ilo->framebuffer.cbufs[i];
+ for (i = 0; i < ilo->fb.state.nr_cbufs; i++) {
+ const struct pipe_surface *surface = ilo->fb.state.cbufs[i];
assert(surface);
surface_state[i] =
struct pipe_surface null_surface;
memset(&null_surface, 0, sizeof(null_surface));
- null_surface.width = ilo->framebuffer.width;
- null_surface.height = ilo->framebuffer.height;
+ null_surface.width = ilo->fb.state.width;
+ null_surface.height = ilo->fb.state.height;
surface_state[i] =
p->gen6_surf_SURFACE_STATE(p->dev, &null_surface, p->cp);
* sampler views (vs, fs)
* constant buffers (vs, fs)
*/
- count = ilo->framebuffer.nr_cbufs;
+ count = ilo->fb.state.nr_cbufs;
if (ilo->gs)
count += ilo->gs->info.stream_output.num_outputs;
gen7_wa_pipe_control_cs_stall(p, true, true);
p->gen7_3DSTATE_SF(p->dev,
- &ilo->rasterizer->state, ilo->framebuffer.zsbuf, p->cp);
+ &ilo->rasterizer->state, ilo->fb.state.zsbuf, p->cp);
}
}
if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
DIRTY(RASTERIZER)) {
const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
- const bool cc_may_kill = (ilo->depth_stencil_alpha->alpha.enabled ||
- ilo->blend->alpha_to_coverage);
+ const bool cc_may_kill = (ilo->dsa->state.alpha.enabled ||
+ ilo->blend->state.alpha_to_coverage);
if (fs)
assert(!fs->pcb.clip_state_size);
const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
const int num_samplers =
ilo->samplers[PIPE_SHADER_FRAGMENT].num_samplers;
- const bool dual_blend = (!ilo->blend->logicop_enable &&
- ilo->blend->rt[0].blend_enable &&
- util_blend_state_is_dual(ilo->blend, 0));
+ const bool dual_blend =
+ (!ilo->blend->state.logicop_enable &&
+ ilo->blend->state.rt[0].blend_enable &&
+ util_blend_state_is_dual(&ilo->blend->state, 0));
if (fs)
assert(!fs->pcb.clip_state_size);
const bool hiz = false;
p->gen7_3DSTATE_DEPTH_BUFFER(p->dev,
- ilo->framebuffer.zsbuf,
- ilo->depth_stencil_alpha,
- hiz, p->cp);
+ ilo->fb.state.zsbuf, &ilo->dsa->state, hiz, p->cp);
p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
- (hiz) ? ilo->framebuffer.zsbuf : NULL, p->cp);
+ (hiz) ? ilo->fb.state.zsbuf : NULL, p->cp);
- p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->framebuffer.zsbuf, p->cp);
+ p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
/* TODO */
p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
/* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
const uint32_t *packed_sample_pos;
- int num_samples = 1;
gen7_wa_pipe_control_cs_stall(p, true, true);
- if (ilo->framebuffer.nr_cbufs)
- num_samples = ilo->framebuffer.cbufs[0]->texture->nr_samples;
-
packed_sample_pos =
- (num_samples > 4) ? p->packed_sample_position_8x :
- (num_samples > 1) ? &p->packed_sample_position_4x :
+ (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
+ (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
&p->packed_sample_position_1x;
- p->gen6_3DSTATE_MULTISAMPLE(p->dev, num_samples, packed_sample_pos,
+ p->gen6_3DSTATE_MULTISAMPLE(p->dev,
+ ilo->fb.num_samples, packed_sample_pos,
ilo->rasterizer->state.half_pixel_center, p->cp);
p->gen7_3DSTATE_SAMPLE_MASK(p->dev,
- (num_samples > 1) ? ilo->sample_mask : 0x1,
- num_samples, p->cp);
+ (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
+ ilo->fb.num_samples, p->cp);
}
}
* sampler views (vs, fs)
* constant buffers (vs, fs)
*/
- count = ilo->framebuffer.nr_cbufs;
+ count = ilo->fb.state.nr_cbufs;
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
count += ilo->sampler_views[shader_type].num_views;
count += ilo->constant_buffers[shader_type].num_buffers;
util_blitter_save_so_targets(ilo->blitter, ilo->so.count, ilo->so.states);
util_blitter_save_fragment_shader(ilo->blitter, ilo->fs);
- util_blitter_save_depth_stencil_alpha(ilo->blitter,
- ilo->depth_stencil_alpha);
- util_blitter_save_blend(ilo->blitter, ilo->blend);
+ util_blitter_save_depth_stencil_alpha(ilo->blitter, (void *) ilo->dsa);
+ util_blitter_save_blend(ilo->blitter, (void *) ilo->blend);
/* undocumented? */
util_blitter_save_viewport(ilo->blitter, &ilo->viewport.states[0]);
util_blitter_save_rasterizer(ilo->blitter, (void *) ilo->rasterizer);
break;
case ILO_BLITTER_CLEAR_SURFACE:
- util_blitter_save_framebuffer(ilo->blitter, &ilo->framebuffer);
+ util_blitter_save_framebuffer(ilo->blitter, &ilo->fb.state);
break;
case ILO_BLITTER_BLIT:
util_blitter_save_rasterizer(ilo->blitter, (void *) ilo->rasterizer);
- util_blitter_save_framebuffer(ilo->blitter, &ilo->framebuffer);
+ util_blitter_save_framebuffer(ilo->blitter, &ilo->fb.state);
util_blitter_save_fragment_sampler_states(ilo->blitter,
ilo->samplers[PIPE_SHADER_FRAGMENT].num_samplers,
ilo_blitter_begin(ilo, ILO_BLITTER_CLEAR);
util_blitter_clear(ilo->blitter,
- ilo->framebuffer.width, ilo->framebuffer.height,
- ilo->framebuffer.nr_cbufs, buffers,
- (ilo->framebuffer.nr_cbufs) ? ilo->framebuffer.cbufs[0]->format :
- PIPE_FORMAT_NONE,
+ ilo->fb.state.width, ilo->fb.state.height,
+ ilo->fb.state.nr_cbufs, buffers,
+ (ilo->fb.state.nr_cbufs) ? ilo->fb.state.cbufs[0]->format :
+ PIPE_FORMAT_NONE,
color, depth, stencil);
ilo_blitter_end(ilo);
struct pipe_poly_stipple poly_stipple;
unsigned sample_mask;
- struct pipe_blend_state *blend;
- struct pipe_depth_stencil_alpha_state *depth_stencil_alpha;
+ const struct ilo_dsa_state *dsa;
+ struct pipe_stencil_ref stencil_ref;
+ const struct ilo_blend_state *blend;
+ struct pipe_blend_color blend_color;
+ struct ilo_fb_state fb;
+
struct ilo_shader_state *fs;
struct ilo_shader_state *vs;
struct ilo_shader_state *gs;
- struct pipe_blend_color blend_color;
- struct pipe_stencil_ref stencil_ref;
- struct pipe_framebuffer_state framebuffer;
-
struct {
struct pipe_sampler_state *samplers[ILO_MAX_SAMPLERS];
unsigned num_samplers;
struct pipe_rasterizer_state state;
};
+struct ilo_dsa_state {
+ struct pipe_depth_stencil_alpha_state state;
+};
+
+struct ilo_blend_state {
+ struct pipe_blend_state state;
+};
+
+struct ilo_fb_state {
+ struct pipe_framebuffer_state state;
+
+ unsigned num_samples;
+};
+
#endif /* ILO_GPE_H */
static uint32_t
gen6_emit_BLEND_STATE(const struct ilo_dev_info *dev,
const struct pipe_blend_state *blend,
- const struct pipe_framebuffer_state *framebuffer,
+ const struct ilo_fb_state *fb,
const struct pipe_alpha_state *alpha,
struct ilo_cp *cp)
{
*
* "The blend state is stored as an array of up to 8 elements..."
*/
- num_targets = framebuffer->nr_cbufs;
+ num_targets = fb->state.nr_cbufs;
assert(num_targets <= 8);
if (!num_targets) {
for (i = 0; i < num_targets; i++) {
const int target = (blend->independent_blend_enable) ? i : 0;
const struct pipe_rt_blend_state *rt = &blend->rt[target];
- const int num_samples = (target < framebuffer->nr_cbufs) ?
- framebuffer->cbufs[target]->texture->nr_samples : 1;
+ const int num_samples = fb->num_samples;
const struct util_format_description *format_desc =
- (target < framebuffer->nr_cbufs) ?
- util_format_description(framebuffer->cbufs[target]->format) : NULL;
+ (target < fb->state.nr_cbufs) ?
+ util_format_description(fb->state.cbufs[target]->format) : NULL;
bool rt_is_unorm, rt_is_pure_integer, rt_dst_alpha_forced_one;
rt_is_unorm = true;
const struct pipe_depth_stencil_alpha_state *dsa,
struct ilo_cp *cp)
{
+ const struct pipe_depth_state *depth = &dsa->depth;
+ const struct pipe_stencil_state *stencil0 = &dsa->stencil[0];
+ const struct pipe_stencil_state *stencil1 = &dsa->stencil[1];
const int state_align = 64 / 4;
const int state_len = 3;
uint32_t state_offset, *dw;
*
* TODO We do not check these yet.
*/
- if (dsa->stencil[0].enabled) {
- const struct pipe_stencil_state *stencil = &dsa->stencil[0];
-
+ if (stencil0->enabled) {
dw[0] = 1 << 31 |
- gen6_translate_dsa_func(stencil->func) << 28 |
- gen6_translate_pipe_stencil_op(stencil->fail_op) << 25 |
- gen6_translate_pipe_stencil_op(stencil->zfail_op) << 22 |
- gen6_translate_pipe_stencil_op(stencil->zpass_op) << 19;
- if (stencil->writemask)
+ gen6_translate_dsa_func(stencil0->func) << 28 |
+ gen6_translate_pipe_stencil_op(stencil0->fail_op) << 25 |
+ gen6_translate_pipe_stencil_op(stencil0->zfail_op) << 22 |
+ gen6_translate_pipe_stencil_op(stencil0->zpass_op) << 19;
+ if (stencil0->writemask)
dw[0] |= 1 << 18;
- dw[1] = stencil->valuemask << 24 |
- stencil->writemask << 16;
-
- if (dsa->stencil[1].enabled) {
- stencil = &dsa->stencil[1];
+ dw[1] = stencil0->valuemask << 24 |
+ stencil0->writemask << 16;
+ if (stencil1->enabled) {
dw[0] |= 1 << 15 |
- gen6_translate_dsa_func(stencil->func) << 12 |
- gen6_translate_pipe_stencil_op(stencil->fail_op) << 9 |
- gen6_translate_pipe_stencil_op(stencil->zfail_op) << 6 |
- gen6_translate_pipe_stencil_op(stencil->zpass_op) << 3;
- if (stencil->writemask)
+ gen6_translate_dsa_func(stencil1->func) << 12 |
+ gen6_translate_pipe_stencil_op(stencil1->fail_op) << 9 |
+ gen6_translate_pipe_stencil_op(stencil1->zfail_op) << 6 |
+ gen6_translate_pipe_stencil_op(stencil1->zpass_op) << 3;
+ if (stencil1->writemask)
dw[0] |= 1 << 18;
- dw[1] |= stencil->valuemask << 8 |
- stencil->writemask;
+ dw[1] |= stencil1->valuemask << 8 |
+ stencil1->writemask;
}
}
else {
*
* TODO We do not check these yet.
*/
- dw[2] = dsa->depth.enabled << 31 |
- dsa->depth.writemask << 26;
- if (dsa->depth.enabled)
- dw[2] |= gen6_translate_dsa_func(dsa->depth.func) << 27;
+ dw[2] = depth->enabled << 31 |
+ depth->writemask << 26;
+ if (depth->enabled)
+ dw[2] |= gen6_translate_dsa_func(depth->func) << 27;
else
dw[2] |= BRW_COMPAREFUNCTION_ALWAYS << 27;
typedef uint32_t
(*ilo_gpe_gen6_BLEND_STATE)(const struct ilo_dev_info *dev,
const struct pipe_blend_state *blend,
- const struct pipe_framebuffer_state *framebuffer,
+ const struct ilo_fb_state *fb,
const struct pipe_alpha_state *alpha,
struct ilo_cp *cp);
variant->u.fs.flatshade =
(info->has_color_interp && ilo->rasterizer->state.flatshade);
variant->u.fs.fb_height = (info->has_pos) ?
- ilo->framebuffer.height : 1;
- variant->u.fs.num_cbufs = ilo->framebuffer.nr_cbufs;
+ ilo->fb.state.height : 1;
+ variant->u.fs.num_cbufs = ilo->fb.state.nr_cbufs;
break;
default:
assert(!"unknown shader type");
case PIPE_SHADER_FRAGMENT:
variant->u.fs.flatshade = false;
variant->u.fs.fb_height = (info->has_pos) ?
- ilo->framebuffer.height : 1;
+ ilo->fb.state.height : 1;
variant->u.fs.num_cbufs = 1;
break;
default:
ilo_create_blend_state(struct pipe_context *pipe,
const struct pipe_blend_state *state)
{
- struct pipe_blend_state *blend;
+ struct ilo_blend_state *blend;
- blend = MALLOC_STRUCT(pipe_blend_state);
+ blend = MALLOC_STRUCT(ilo_blend_state);
assert(blend);
- *blend = *state;
+ blend->state = *state;
return blend;
}
ilo_create_depth_stencil_alpha_state(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *state)
{
- struct pipe_depth_stencil_alpha_state *dsa;
+ struct ilo_dsa_state *dsa;
- dsa = MALLOC_STRUCT(pipe_depth_stencil_alpha_state);
+ dsa = MALLOC_STRUCT(ilo_dsa_state);
assert(dsa);
- *dsa = *state;
+ dsa->state = *state;
return dsa;
}
{
struct ilo_context *ilo = ilo_context(pipe);
- ilo->depth_stencil_alpha = state;
+ ilo->dsa = state;
ilo->dirty |= ILO_DIRTY_DEPTH_STENCIL_ALPHA;
}
{
struct ilo_context *ilo = ilo_context(pipe);
- util_copy_framebuffer_state(&ilo->framebuffer, state);
+ util_copy_framebuffer_state(&ilo->fb.state, state);
+
+ if (state->nr_cbufs)
+ ilo->fb.num_samples = state->cbufs[0]->texture->nr_samples;
+ else if (state->zsbuf)
+ ilo->fb.num_samples = state->zsbuf->texture->nr_samples;
+ else
+ ilo->fb.num_samples = 1;
+
+ if (!ilo->fb.num_samples)
+ ilo->fb.num_samples = 1;
ilo->dirty |= ILO_DIRTY_FRAMEBUFFER;
}
projects / mesa.git / commitdiff