ISA: Get rid of old, unused utility functions cluttering up the ISAs.

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 609b45957f8339d768694b6661bf5c4a218bef70..0db75df461c89f644c1a0525e09dee4cfc5211d7 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -66,53 +66,6 @@ initCPU(ThreadContext *tc, int cpuId)
     delete reset;
 }
 
-
-template <class CPU>
-void
-processInterrupts(CPU *cpu)
-{
-    //Check if there are any outstanding interrupts
-    //Handle the interrupts
-    int ipl = 0;
-    int summary = 0;
-
-    if (cpu->readMiscRegNoEffect(IPR_ASTRR))
-        panic("asynchronous traps not implemented\n");
-
-    if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
-        for (int i = INTLEVEL_SOFTWARE_MIN;
-             i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    uint64_t interrupts = cpu->intr_status();
-
-    if (interrupts) {
-        for (int i = INTLEVEL_EXTERNAL_MIN;
-             i < INTLEVEL_EXTERNAL_MAX; i++) {
-            if (interrupts & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = i;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
-        cpu->setMiscRegNoEffect(IPR_ISR, summary);
-        cpu->setMiscRegNoEffect(IPR_INTID, ipl);
-        cpu->trap(new InterruptFault);
-        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
-    }
-
-}
-
 template <class CPU>
 void
 zeroRegisters(CPU *cpu)

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 0b994d324b381b5f07aa559faf92fdca1e026f21..281fc4492ff4b93f6e1f033311da149e54490b58 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -49,68 +49,6 @@ inUserMode(ThreadContext *tc)
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-inline bool
-isCallerSaveIntegerRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
-}
-
-inline bool
-isCalleeSaveIntegerRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return reg >= 9 && reg <= 15;
-}
-
-inline bool
-isCallerSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
-
-inline bool
-isCalleeSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
-
-inline Addr
-alignAddress(const Addr &addr, unsigned int nbytes)
-{
-    return (addr & ~(nbytes - 1));
-}
-
-// Instruction address compression hooks
-inline Addr
-realPCToFetchPC(const Addr &addr)
-{
-    return addr;
-}
-
-inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
-    return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-inline size_t
-fetchInstSize()
-{
-    return sizeof(MachInst);
-}
-
-inline MachInst
-makeRegisterCopy(int dest, int src)
-{
-    panic("makeRegisterCopy not implemented");
-    return 0;
-}
-
 /**
  * Function to insure ISA semantics about 0 registers.
  * @param tc The thread context.
@@ -150,13 +88,6 @@ RoundPage(Addr addr)
 void initIPRs(ThreadContext *tc, int cpuId);
 #if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
-
-/**
- * Function to check for and process any interrupts.
- * @param tc The thread context.
- */
-template <class TC>
-void processInterrupts(TC *tc);
 #endif
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 6ee2fb3257c9606b6fc2fdd64b0c983a56f1489e..076468e0d3308c7e2769f27c9b23d7b14166fe4c 100644 (file)
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -96,25 +96,6 @@ namespace ArmISA {
     template <class TC>
     void zeroRegisters(TC *tc);
 
-    // Instruction address compression hooks
-    static inline Addr realPCToFetchPC(const Addr &addr) {
-        return addr;
-    }
-
-    static inline Addr fetchPCToRealPC(const Addr &addr) {
-        return addr;
-    }
-
-    // the size of "fetched" instructions
-    static inline size_t fetchInstSize() {
-        return sizeof(MachInst);
-    }
-
-    static inline MachInst makeRegisterCopy(int dest, int src) {
-        panic("makeRegisterCopy not implemented");
-        return 0;
-    }
-
     inline void startupCPU(ThreadContext *tc, int cpuId)
     {
         tc->activate(0);

diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
index 14f4186e326efd780a809737fab9cb4bd7ed858b..31d47c842d1cc9bf6befe6a6f4f4d85e01ee3f6d 100755 (executable)
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/mips/mips_core_specific.cc
@@ -43,9 +43,4 @@ void
 MipsISA::initCPU(ThreadContext *tc, int cpuId)
 {}
 
-template <class CPU>
-void
-MipsISA::processInterrupts(CPU *cpu)
-{}
-
 #endif // FULL_SYSTEM || BARE_IRON

diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh
index 0d19bf944d62528c497d01db872bcfed1fbb7155..bd66e049f23148c99003e4d2639ba1a848e3eaa5 100644 (file)
--- a/src/arch/mips/mips_core_specific.hh
+++ b/src/arch/mips/mips_core_specific.hh
@@ -37,13 +37,6 @@ class ThreadContext;
 
 namespace MipsISA {
     void initCPU(ThreadContext *tc, int cpuId);
-
-    /**
-     * Function to check for and process any interrupts.
-     * @param tc The thread context.
-     */
-    template <class CPU>
-    void processInterrupts(CPU *cpu);
 };
 
 #endif // __ARCH_MIPS_CORE_SPECIFIC_HH__

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 1e58238e980721c199ee83d40964bec60c806a6f..f827e9b33a80f7e3aff9867ed6ea5ad4c33ff7a1 100644 (file)
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -79,30 +79,6 @@ inUserMode(ThreadContext *tc)
     }
 }
 
-// Instruction address compression hooks
-static inline Addr realPCToFetchPC(const Addr &addr) {
-    return addr;
-}
-
-static inline Addr fetchPCToRealPC(const Addr &addr) {
-    return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-static inline size_t fetchInstSize() {
-    return sizeof(MachInst);
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Register File Utility Functions
-//
-static inline MachInst makeRegisterCopy(int dest, int src) {
-    panic("makeRegisterCopy not implemented");
-    return 0;
-}
-
 template <class CPU>
 void zeroRegisters(CPU *cpu);
 

diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 6263635e9710af6fb1d0bf599a4f29dc6c9815c9..aff6fda78ad3737cf1591b96be5cc26b82b74b4e 100644 (file)
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -61,33 +61,6 @@ namespace PowerISA {
 template <class TC>
 void zeroRegisters(TC *tc);
 
-// Instruction address compression hooks
-static inline Addr
-realPCToFetchPC(const Addr &addr)
-{
-    return addr;
-}
-
-static inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
-    return addr;
-}
-
-// the size of "fetched" instructions
-static inline size_t
-fetchInstSize()
-{
-    return sizeof(MachInst);
-}
-
-static inline MachInst
-makeRegisterCopy(int dest, int src)
-{
-    panic("makeRegisterCopy not implemented");
-    return 0;
-}
-
 inline void
 startupCPU(ThreadContext *tc, int cpuId)
 {

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 064af9c6ab726e7c60476f59dfbffecef122f60f..fe3082c5e6cc03af4714203b8eca4d33dd231ece 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,44 +50,6 @@ namespace SparcISA
                  (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
     }
 
-    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCallerSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize()
-    {
-        return sizeof(MachInst);
-    }
-
     /**
      * Function to insure ISA semantics about 0 registers.
      * @param tc The thread context.

diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index d833531624543c910e53f07b49ba44847f122bed..4c987faee5f5de3a01c41c98416304bf3ad63666 100644 (file)
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -85,44 +85,6 @@ namespace X86ISA
 #endif
     }
 
-    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCallerSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize()
-    {
-        return sizeof(MachInst);
-    }
-
     /**
      * Function to insure ISA semantics about 0 registers.
      * @param tc The thread context.

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 425c34428e3ff4b55d96af89bf5a75b5046293f6..d881c291fc73757a78b637653ba470ff6ac0e0a9 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -290,7 +290,6 @@ class DefaultFetch
     /** Align a PC to the start of an I-cache block. */
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 

diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 3809db00db3aee572ac0a106a77f3740a3153069..892e279c0911d8ad663bcc6529d6bc71206462aa 100644 (file)
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -167,7 +167,6 @@ class FrontEnd
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }