(no commit message)

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 182e9bea676de8a0c761ac2d45783468c5cc9e43..80f3d08fe92c21ab85b9b1ba8d7c4c1785e046f8 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -114,10 +114,12 @@ Horizontal-First Mode:
   destinations.  Strict Program Order is required in full.
 
 *Implementor's note: the cost of Vertical-First Mode in an Embedded design
-of storing four 64-bit in-flight elements may be too high. If this is the
+of storing four 64-bit in-flight elements may be considered
+too high. If this is the
 case it is acceptable to throw an Illegal Instruction Trap, and emulate
 the instruction in software. Performance will obviously be adversely affected.
-See [[sv/compliancy_levels]]*
+See [[sv/compliancy_levels]]*: all aspects of
+Swizzle are entirely optional in hardware at the Embedded Level.
 
 # RM Mode Concept: