inorder: simplify handling of split accesses

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index bd93d44628b7a19f73d67fcfa15d3e0b63ec5b80..9352d8e9d2f7dc1b6e3692a1404a5e0c0312522a 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -447,12 +447,16 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
 
         if ( inst->isLoad() ) {
             M.needs(DCache, CacheUnit::InitiateReadData);
+            if (inst->splitInst)
+                M.needs(DCache, CacheUnit::InitSecondSplitRead);
         } else if ( inst->isStore() ) {
             if ( inst->numSrcRegs() >= 2 ) {
                 M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
             }
             M.needs(AGEN, AGENUnit::GenerateAddr);
             M.needs(DCache, CacheUnit::InitiateWriteData);
+            if (inst->splitInst)
+                M.needs(DCache, CacheUnit::InitSecondSplitWrite);
         }
     }
 
@@ -460,8 +464,12 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
     if (!inst->isNonSpeculative()) {
         if ( inst->isLoad() ) {
             W.needs(DCache, CacheUnit::CompleteReadData);
+            if (inst->splitInst)
+                W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
         } else if ( inst->isStore() ) {
             W.needs(DCache, CacheUnit::CompleteWriteData);
+            if (inst->splitInst)
+                W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
         }
     } else {
         // Finally, Execute Speculative Data
@@ -469,14 +477,22 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
             if (inst->isLoad()) {
                 W.needs(AGEN, AGENUnit::GenerateAddr);
                 W.needs(DCache, CacheUnit::InitiateReadData);
+                if (inst->splitInst)
+                    W.needs(DCache, CacheUnit::InitSecondSplitRead);
                 W.needs(DCache, CacheUnit::CompleteReadData);
+                if (inst->splitInst)
+                    W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
             } else if (inst->isStore()) {
                 if ( inst->numSrcRegs() >= 2 ) {
                     W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
                 }
                 W.needs(AGEN, AGENUnit::GenerateAddr);
                 W.needs(DCache, CacheUnit::InitiateWriteData);
+                if (inst->splitInst)
+                    W.needs(DCache, CacheUnit::InitSecondSplitWrite);
                 W.needs(DCache, CacheUnit::CompleteWriteData);
+                if (inst->splitInst)
+                    W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
             }
         } else {
             W.needs(ExecUnit, ExecutionUnit::ExecuteInst);

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index a468f8fa8095e1642d9ad422f0f9069476b958ed..a1fc2de52243862539db3ebb729b7e4fd5b80e26 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -344,6 +344,7 @@ class InOrderCPU : public BaseCPU
     static const uint8_t INST_NONSPEC                       = 22;
     static const uint8_t INST_DEST_REGS                     = 18;
     static const uint8_t INST_SRC_REGS                      = 14;
+    static const uint8_t INST_SPLIT_DATA                    = 13;
 
     inline SkedID genSkedID(DynInstPtr inst)
     {
@@ -354,7 +355,8 @@ class InOrderCPU : public BaseCPU
             (inst->isControl() << INST_CONTROL) |
             (inst->isNonSpeculative() << INST_NONSPEC) |
             (inst->numDestRegs() << INST_DEST_REGS) |
-            (inst->numSrcRegs() << INST_SRC_REGS);
+            (inst->numSrcRegs() << INST_SRC_REGS) |
+            (inst->splitInst << INST_SPLIT_DATA);
         return id;
     }
 

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 620ba06c15eb1b825640d4d9ec4f6dee33e47350..c38e5541decc5da515c8ff698809f6e7e46d6164 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -488,49 +488,33 @@ CacheUnit::read(DynInstPtr inst, Addr addr,
 
     
     if (secondAddr > addr && !inst->split2ndAccess) {
-        DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
-                "(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
-        
-        // Save All "Total" Split Information
-        // ==============================
-        inst->splitInst = true;        
-        inst->splitMemData = new uint8_t[size];
-        
-        if (!inst->splitInstSked) {
-            assert(0 && "Split Requests Not Supported for Now...");
 
-            // Schedule Split Read/Complete for Instruction
-            // ==============================
-            int stage_num = cache_req->getStageNum();
-            RSkedPtr inst_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
-                inst->backSked : inst->frontSked;
+        if (!inst->splitInst) {
+            DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
+                    "(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
 
-            // this is just an arbitrarily high priority to ensure that this
-            // gets pushed to the back of the list
-            int stage_pri = 20;
-        
-            int isplit_cmd = CacheUnit::InitSecondSplitRead;
-            inst_sked->push(new
-                                ScheduleEntry(stage_num,
-                                              stage_pri,
-                                              cpu->resPool->getResIdx(DCache),
-                                              isplit_cmd,
-                                              1));
+            unsigned stage_num = cache_req->getStageNum();
+            unsigned cmd = inst->curSkedEntry->cmd;
 
-            int csplit_cmd = CacheUnit::CompleteSecondSplitRead;
-            inst_sked->push(new
-                                ScheduleEntry(stage_num + 1,
-                                              1/*stage_pri*/,
-                                              cpu->resPool->getResIdx(DCache),
-                                              csplit_cmd,
-                                              1));
-            inst->splitInstSked = true;
+            // 1. Make A New Inst. Schedule w/Split Read/Complete Entered on
+            // the schedule
+            // ==============================
+            // 2. Reassign curSkedPtr to current command (InitiateRead) on new
+            // schedule
+            // ==============================
+            inst->splitInst = true;
+            inst->setBackSked(cpu->createBackEndSked(inst));
+            inst->curSkedEntry = inst->backSked->find(stage_num, cmd);
         } else {
             DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] Retrying Split Read "
                     "Access (1 of 2) for (%#x, %#x).\n", inst->readTid(),
                     inst->seqNum, addr, secondAddr);
         }
 
+        // Save All "Total" Split Information
+        // ==============================
+        inst->splitMemData = new uint8_t[size];
+
         // Split Information for First Access
         // ==============================
         size = secondAddr - addr;

diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index d8bf8790bd6108e1fb902432d371d0c1ec5cc9e6..64299802127314fc067c3b04ee3ab72aed1f0417 100644 (file)
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -198,7 +198,7 @@ UseDefUnit::execute(int slot_idx)
                         uniqueIntRegMap[flat_idx] = true;
 
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Int Reg %i"
-                                " (%i) from Register File:%i.\n",
+                                " (%i) from Register File:0x%x.\n",
                                 tid, seq_num,
                                 reg_idx, flat_idx,
                                 cpu->readIntReg(flat_idx,inst->readTid()));
@@ -232,7 +232,7 @@ UseDefUnit::execute(int slot_idx)
                     {
                         uniqueMiscRegMap[flat_idx] = true;
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
-                                " (%i) from Register File:%i.\n",
+                                " (%i) from Register File:0x%x.\n",
                                 tid, seq_num,
                                 reg_idx - Ctrl_Base_DepTag, flat_idx,
                                 cpu->readMiscReg(flat_idx,
@@ -265,7 +265,7 @@ UseDefUnit::execute(int slot_idx)
                         {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
                                     " reg %i (%i), value 0x%x from "
-                                    "[sn:%i] to [sn:%i] source #%i.\n",
+                                    "[sn:%i] to [sn:%i] source #%x.\n",
                                     tid, reg_idx, flat_idx,
                                     forward_inst->readIntResult(dest_reg_idx),
                                     forward_inst->seqNum,