cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT"));
cell->attributes = std::move(st.carry->attributes);
+ auto it = cell->attributes.find(ID::keep);
+ if (it != cell->attributes.end() && !it->second.as_bool())
+ cell->attributes.erase(it);
cell->attributes.insert(st.lut->attributes.begin(), st.lut->attributes.end());
pm.autoremove(st.carry);
log("into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology\n");
log("mapping.");
log("\n");
+ log("Attributes on both cells will be merged, with SB_CARRY attributes having priority\n");
+ log("over SB_LUT4 attributes, except when (* keep *) attributes present on the SB_CARRY4\n");
+ log("that logically evaluate to false will be dropped (thus allowing the keep attribute,\n");
+ log("if any, on the SB_LUT4 to be adopted).\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
design -reset
read_verilog <<EOT
module top(input A, B, CI, output O, CO);
- (* foo = "bar", answer = 42 *)
+ (* foo = "bar", answer = 42, keep=0 *)
SB_CARRY carry (
.I0(A),
.I1(B),
ice40_wrapcarry
select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
-select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i
techmap -map +/ice40/cells_map.v
#TODO: Check unwrapped attributes