Changed a lot of code to the new RTLIL::Wire constructors

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index dba301f462682638b35819e3e0deb70623bf8cca..3bc9b06eec6ef48d918557228e0f0413f863afef 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -290,16 +290,16 @@ struct AST_INTERNAL::ProcessGenerator
                        if (chunk.wire == NULL)
                                continue;
 
-                       RTLIL::Wire *wire = new RTLIL::Wire;
-                       wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
+                       std::string wire_name;
                        do {
-                               wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
+                               wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
                                                chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
                                if (chunk.wire->name.find('$') != std::string::npos)
-                                       wire->name += stringf("$%d", RTLIL::autoidx++);
-                       } while (current_module->wires.count(wire->name) > 0);
-                       wire->width = chunk.width;
-                       current_module->wires[wire->name] = wire;
+                                       wire_name += stringf("$%d", RTLIL::autoidx++);
+                       } while (current_module->wires.count(wire_name) > 0);
+
+                       RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
+                       wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
 
                        chunk.wire = wire;
                        chunk.offset = 0;
@@ -792,15 +792,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                range_right = tmp;
                        }
 
-                       RTLIL::Wire *wire = new RTLIL::Wire;
+                       RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
                        wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
-                       wire->name = str;
-                       wire->width = range_left - range_right + 1;
                        wire->start_offset = range_right;
                        wire->port_id = port_id;
                        wire->port_input = is_input;
                        wire->port_output = is_output;
-                       current_module->wires[wire->name] = wire;
 
                        for (auto &attr : attributes) {
                                if (attr.second->type != AST_CONSTANT)
@@ -873,14 +870,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        RTLIL::SigChunk chunk;
 
                        if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) {
-                               RTLIL::Wire *wire = new RTLIL::Wire;
+                               RTLIL::Wire *wire = current_module->addWire(str);
                                wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
                                wire->name = str;
                                if (flag_autowire)
                                        log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
                                else
                                        log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
-                               current_module->wires[str] = wire;
                        }
                        else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
                                if (id2ast->children[0]->type != AST_CONSTANT)

diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index 09437a0aa2bc0ab3db52086db2393cb73edb48fb..20490e0d2f384a283134755854a4fe18348dadf7 100644 (file)
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -121,14 +121,13 @@ autoidx_stmt:
 
 wire_stmt:
        TOK_WIRE {
-               current_wire = new RTLIL::Wire;
+               current_wire = current_module->addWire("$__ilang_frontend_tmp__");
                current_wire->attributes = attrbuf;
                attrbuf.clear();
        } wire_options TOK_ID EOL {
                if (current_module->wires.count($4) != 0)
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
-               current_wire->name = $4;
-               current_module->wires[$4] = current_wire;
+               current_module->rename(current_wire, $4);
                free($4);
        };
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 059357d21dd8e9daf42cc19ebe3b4c7665eaee34..930e8a7198ee1db7050ceceed2e6d272f271a4c1 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -827,6 +827,46 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
        cells[cell->name] = cell;
 }
 
+namespace {
+       struct DeleteWireWorker
+       {
+               RTLIL::Module *module;
+               const std::set<RTLIL::Wire*> *wires_p;
+
+               void operator()(RTLIL::SigSpec &sig) {
+                       std::vector<RTLIL::SigChunk> chunks = sig;
+                       for (auto &c : chunks)
+                               if (c.wire != NULL && wires_p->count(c.wire)) {
+                                       c.wire = module->addWire(NEW_ID, c.width);
+                                       c.offset = 0;
+                               }
+                       sig = chunks;
+               }
+       };
+}
+
+#if 0
+void RTLIL::Module::remove(RTLIL::Wire *wire)
+{
+       std::set<RTLIL::Wire*> wires;
+       wires.insert(wire);
+       remove(wires);
+}
+#endif
+
+void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
+{
+       DeleteWireWorker delete_wire_worker;
+       delete_wire_worker.module = this;
+       delete_wire_worker.wires_p = &wires;
+       rewrite_sigspecs(delete_wire_worker);
+
+       for (auto &it : wires) {
+               this->wires.erase(it->name);
+               delete it;
+       }
+}
+
 void RTLIL::Module::remove(RTLIL::Cell *cell)
 {
        assert(cells.count(cell->name) != 0);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 73d3727cec294eb8abe6e2444bf25610785ab8b7..f43e7b670ceb9a49fbff36675ec74a48c2bed3f0 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -299,6 +299,9 @@ struct RTLIL::Module
 
        void add(RTLIL::Wire *wire);
        void add(RTLIL::Cell *cell);
+
+       // Removing wires is expensive. If you have to remove wires, remove them all at once.
+       void remove(const std::set<RTLIL::Wire*> &wires);
        void remove(RTLIL::Cell *cell);
 
        void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 4d9a6c136c3b46638c005d5b3f3963ed2b7c0e34..41cfe88f6f1d8b4d88ea5635a671ff770ab7192d 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -313,11 +313,9 @@ static void handle_loops()
                                continue;
                        }
 
-                       RTLIL::Wire *wire = new RTLIL::Wire;
                        std::stringstream sstr;
                        sstr << "$abcloop$" << (RTLIL::autoidx++);
-                       wire->name = sstr.str();
-                       module->wires[wire->name] = wire;
+                       RTLIL::Wire *wire = module->addWire(sstr.str());
 
                        bool first_line = true;
                        for (int id2 : edges[id1]) {
@@ -691,9 +689,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        log_error("ABC output file does not contain a module `netlist'.\n");
                for (auto &it : mapped_mod->wires) {
                        RTLIL::Wire *w = it.second;
-                       RTLIL::Wire *wire = new RTLIL::Wire;
-                       wire->name = remap_name(w->name);
-                       module->wires[wire->name] = wire;
+                       RTLIL::Wire *wire = module->addWire(remap_name(w->name));
                        design->select(module, wire);
                }
 

diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 45a9ac76596c1daece8813c89568ba2b98cbfb80..e86afa1b769e7515d9fb05094f3c580828d004c4 100644 (file)
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -98,14 +98,12 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
                        if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
                                char *p;
                                while ((p = strtok(NULL, " \t\r\n")) != NULL) {
-                                       RTLIL::Wire *wire = new RTLIL::Wire;
-                                       wire->name = stringf("\\%s", p);
+                                       RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
                                        wire->port_id = ++port_count;
                                        if (!strcmp(cmd, ".inputs"))
                                                wire->port_input = true;
                                        else
                                                wire->port_output = true;
-                                       module->add(wire);
                                }
                                continue;
                        }
@@ -115,17 +113,11 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
                                char *d = strtok(NULL, " \t\r\n");
                                char *q = strtok(NULL, " \t\r\n");
 
-                               if (module->wires.count(RTLIL::escape_id(d)) == 0) {
-                                       RTLIL::Wire *wire = new RTLIL::Wire;
-                                       wire->name = RTLIL::escape_id(d);
-                                       module->add(wire);
-                               }
+                               if (module->wires.count(RTLIL::escape_id(d)) == 0)
+                                       module->addWire(RTLIL::escape_id(d));
 
-                               if (module->wires.count(RTLIL::escape_id(q)) == 0) {
-                                       RTLIL::Wire *wire = new RTLIL::Wire;
-                                       wire->name = RTLIL::escape_id(q);
-                                       module->add(wire);
-                               }
+                               if (module->wires.count(RTLIL::escape_id(q)) == 0)
+                                       module->addWire(RTLIL::escape_id(q));
 
                                RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
                                cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
@@ -162,9 +154,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
                                        if (module->wires.count(stringf("\\%s", p)) > 0) {
                                                wire = module->wires.at(stringf("\\%s", p));
                                        } else {
-                                               wire = new RTLIL::Wire;
-                                               wire->name = stringf("\\%s", p);
-                                               module->add(wire);
+                                               wire = module->addWire(stringf("\\%s", p));
                                        }
                                        input_sig.append(wire);
                                }

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index f94ea639b43a7bfaffa9b292fece64fad5687a8b..7e9ba97ec0de665929efed2a27e0836542882fcc 100644 (file)
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -47,12 +47,9 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
        }
        else
        {
-               wire = new RTLIL::Wire;
-               wire->name = name;
-               wire->width = width;
+               wire = module->addWire(name, width);
                wire->port_input = flag_input;
                wire->port_output = flag_output;
-               module->add(wire);
 
                if (flag_input || flag_output) {
                        wire->port_id = module->wires.size();

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 79b7c3c30f6b66584beaa3e6e81a86a6b6f83c44..df5a3d4b97f77f084be880bbded3badfc93886a5 100644 (file)
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -21,22 +21,6 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
-struct DeleteWireWorker
-{
-       RTLIL::Module *module;
-       std::set<std::string> *delete_wires_p;
-
-       void operator()(RTLIL::SigSpec &sig) {
-               std::vector<RTLIL::SigChunk> chunks = sig;
-               for (auto &c : chunks)
-                       if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
-                               c.wire = module->addWire(NEW_ID, c.width);
-                               c.offset = 0;
-                       }
-               sig = chunks;
-       }
-};
-
 struct DeletePass : public Pass {
        DeletePass() : Pass("delete", "delete objects in the design") { }
        virtual void help()
@@ -106,14 +90,14 @@ struct DeletePass : public Pass {
                                continue;
                        }
 
-                       std::set<std::string> delete_wires;
+                       std::set<RTLIL::Wire*> delete_wires;
                        std::set<RTLIL::Cell*> delete_cells;
                        std::set<std::string> delete_procs;
                        std::set<std::string> delete_mems;
 
                        for (auto &it : module->wires)
                                if (design->selected(module, it.second))
-                                       delete_wires.insert(it.first);
+                                       delete_wires.insert(it.second);
 
                        for (auto &it : module->memories)
                                if (design->selected(module, it.second))
@@ -131,30 +115,21 @@ struct DeletePass : public Pass {
                                if (design->selected(module, it.second))
                                        delete_procs.insert(it.first);
 
-                       DeleteWireWorker delete_wire_worker;
-                       delete_wire_worker.module = module;
-                       delete_wire_worker.delete_wires_p = &delete_wires;
-                       module->rewrite_sigspecs(delete_wire_worker);
-
-                       for (auto &it : delete_wires) {
-                               delete module->wires.at(it);
-                               module->wires.erase(it);
-                       }
-
                        for (auto &it : delete_mems) {
                                delete module->memories.at(it);
                                module->memories.erase(it);
                        }
 
-                       for (auto &it : delete_cells) {
+                       for (auto &it : delete_cells)
                                module->remove(it);
-                       }
 
                        for (auto &it : delete_procs) {
                                delete module->processes.at(it);
                                module->processes.erase(it);
                        }
 
+                       module->remove(delete_wires);
+
                        module->fixup_ports();
                }
 

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 35ce0a1107bcde1724d75dbd3117d210a9cefaac..0b95fe02487885c8a6e85def0da0b4a727b87e90 100644 (file)
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -51,10 +51,7 @@ struct ScatterPass : public Pass {
                        for (auto &c : mod_it.second->cells)
                        for (auto &p : c.second->connections_)
                        {
-                               RTLIL::Wire *wire = new RTLIL::Wire;
-                               wire->name = NEW_ID;
-                               wire->width = p.second.size();
-                               mod_it.second->add(wire);
+                               RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
 
                                if (ct.cell_output(c.second->type, p.first)) {
                                        RTLIL::SigSig sigsig(p.second, wire);

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 28575e7b4bd3ed81cf14af51f1440a2b7925c045..6bffba622409a49cdd74057f799420b2038f0957 100644 (file)
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -28,33 +28,31 @@ struct SplitnetsWorker
 
        void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
        {
-               RTLIL::Wire *new_wire = new RTLIL::Wire;
-
-               new_wire->port_id = wire->port_id;
-               new_wire->port_input = wire->port_input;
-               new_wire->port_output = wire->port_output;
-               new_wire->name = wire->name;
-               new_wire->width = width;
+               std::string new_wire_name = wire->name;
 
                if (format.size() > 0)
-                       new_wire->name += format.substr(0, 1);
+                       new_wire_name += format.substr(0, 1);
 
                if (width > 1) {
-                       new_wire->name += stringf("%d", offset+width-1);
+                       new_wire_name += stringf("%d", offset+width-1);
                        if (format.size() > 2)
-                               new_wire->name += format.substr(2, 1);
+                               new_wire_name += format.substr(2, 1);
                        else
-                               new_wire->name += ":";
+                               new_wire_name += ":";
                }
 
-               new_wire->name += stringf("%d", offset);
+               new_wire_name += stringf("%d", offset);
 
                if (format.size() > 1)
-                       new_wire->name += format.substr(1, 1);
+                       new_wire_name += format.substr(1, 1);
 
-               while (module->count_id(new_wire->name) > 0)
-                       new_wire->name = new_wire->name + "_";
-               module->add(new_wire);
+               while (module->count_id(new_wire_name) > 0)
+                       new_wire_name += "_";
+
+               RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
+               new_wire->port_id = wire->port_id;
+               new_wire->port_input = wire->port_input;
+               new_wire->port_output = wire->port_output;
 
                std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
                splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
@@ -178,10 +176,10 @@ struct SplitnetsPass : public Pass {
 
                        module->rewrite_sigspecs(worker);
 
-                       for (auto &it : worker.splitmap) {
-                               module->wires.erase(it.first->name);
-                               delete it.first;
-                       }
+                       std::set<RTLIL::Wire*> delete_wires;
+                       for (auto &it : worker.splitmap)
+                               delete_wires.insert(it.first);
+                       module->remove(delete_wires);
 
                        module->fixup_ports();
                }

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index ff3ac7608281140db17407ecedf2633888af5ecf..51a4a75e7882bea841496bbbd3047806ce56c42d 100644 (file)
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire)
                RTLIL::Cell *cell = module->cells.at(cellport.first);
                RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
                RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
-               RTLIL::Wire *unconn_wire = new RTLIL::Wire;
-               unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
-               unconn_wire->width = unconn_sig.size();
-               module->wires[unconn_wire->name] = unconn_wire;
+               RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
                port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
        }
 }

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index a22441b4ac92f835aa3d81585c3ae30398a834e8..7ab15954034e75f50986f30d9b26f59af84dcf5c 100644 (file)
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -143,13 +143,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
        // create state register
 
-       RTLIL::Wire *state_wire = new RTLIL::Wire;
-       state_wire->name = fsm_cell->parameters["\\NAME"].decode_string();
-       while (module->count_id(state_wire->name) > 0)
-               state_wire->name += "_";
-       state_wire->width = fsm_data.state_bits;
-       module->add(state_wire);
+       std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
+       while (module->count_id(state_wire_name) > 0)
+               state_wire_name += "_";
 
+       RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
        RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
        RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
@@ -209,10 +207,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
        // generate next_state signal
 
-       RTLIL::Wire *next_state_onehot = new RTLIL::Wire;
-       next_state_onehot->name = NEW_ID;
-       next_state_onehot->width = fsm_data.state_table.size();
-       module->add(next_state_onehot);
+       RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
 
        for (size_t i = 0; i < fsm_data.state_table.size(); i++)
        {
@@ -275,11 +270,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
        // Generate ctrl_out signal
 
-       RTLIL::Wire *ctrl_out_wire = new RTLIL::Wire;
-       ctrl_out_wire->name = NEW_ID;
-       ctrl_out_wire->width = fsm_data.num_outputs;
-       module->add(ctrl_out_wire);
-
        for (int i = 0; i < fsm_data.num_outputs; i++)
        {
                std::map<RTLIL::Const, std::set<int>> pattern_cache;

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 76b667b86a4d88c6920d4c8a573fa247f3bd402c..8c09d2eaaaa127980f7d45609a96e331fd6dbde9 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -118,13 +118,10 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
                design->modules[mod->name] = mod;
 
                for (auto &decl : ports) {
-                       RTLIL::Wire *wire = new RTLIL::Wire;
-                       wire->name = decl.portname;
-                       wire->width = portwidths.at(decl.portname);
+                       RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
                        wire->port_id = decl.index;
                        wire->port_input = decl.input;
                        wire->port_output = decl.output;
-                       mod->add(wire);
                }
 
                for (auto &para : parameters)

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ef4a9f16d5249690c0a22ce5a6072dec3132f64e..e39f96ca818fa21a74bc0774e83a5b4f1d466ef0 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -123,31 +123,37 @@ struct SubmodWorker
                        if (wire->port_output)
                                flags.is_ext_used = true;
 
-                       RTLIL::Wire *new_wire = new RTLIL::Wire;
-                       new_wire->name = wire->name;
-                       new_wire->width = wire->width;
-                       new_wire->start_offset = wire->start_offset;
-                       new_wire->attributes = wire->attributes;
+                       bool new_wire_port_input = false;
+                       bool new_wire_port_output = false;
 
                        if (flags.is_int_driven && flags.is_ext_used)
-                               new_wire->port_output = true;
+                               new_wire_port_output = true;
                        if (flags.is_ext_driven && flags.is_int_used)
-                               new_wire->port_input = true;
+                               new_wire_port_input = true;
 
                        if (flags.is_int_driven && flags.is_ext_driven)
-                               new_wire->port_input = true, new_wire->port_output = true;
-
-                       if (new_wire->port_input || new_wire->port_output) {
-                               new_wire->port_id = port_counter++;
-                               while (new_wire->name[0] == '$') {
-                                       std::string new_wire_name = stringf("\\n%d", auto_name_counter++);
-                                       if (all_wire_names.count(new_wire_name) == 0) {
-                                               all_wire_names.insert(new_wire_name);
-                                               new_wire->name = new_wire_name;
+                               new_wire_port_input = true, new_wire_port_output = true;
+
+                       std::string new_wire_name = wire->name;
+                       if (new_wire_port_input || new_wire_port_output) {
+                               while (new_wire_name[0] == '$') {
+                                       std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
+                                       if (all_wire_names.count(next_wire_name) == 0) {
+                                               all_wire_names.insert(next_wire_name);
+                                               new_wire_name = next_wire_name;
                                        }
                                }
                        }
 
+                       RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
+                       new_wire->port_input = new_wire_port_input;
+                       new_wire->port_output = new_wire_port_output;
+                       new_wire->start_offset = wire->start_offset;
+                       new_wire->attributes = wire->attributes;
+
+                       if (new_wire->port_input || new_wire->port_output)
+                               new_wire->port_id = port_counter++;
+
                        if (new_wire->port_input && new_wire->port_output)
                                log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
                        else if (new_wire->port_input)
@@ -157,7 +163,6 @@ struct SubmodWorker
                        else
                                log("  signal %s: internal\n", wire->name.c_str());
 
-                       new_mod->wires[new_wire->name] = new_wire;
                        flags.new_wire = new_wire;
                }
 

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 999c969b52737c257281e0fb65575acd85337a9d..b63b3aec669875b4bddadae0d03ac32e6afeeb0d 100644 (file)
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -118,18 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
        std::stringstream sstr;
        sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
 
-       RTLIL::Wire *wire = new RTLIL::Wire;
-       wire->name = sstr.str();
-       wire->width = sig.size();
-       module->wires[wire->name] = wire;
-
-       RTLIL::SigSpec newsig(wire);
+       RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
        for (auto &cell_it : module->cells) {
                RTLIL::Cell *cell = cell_it.second;
                if (cell->type == "$dff") {
                        RTLIL::SigSpec new_q = cell->get("\\Q");
-                       new_q.replace(sig, newsig);
+                       new_q.replace(sig, new_sig);
                        cell->set("\\Q", new_q);
                }
        }

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 5b180db620d4e354cf5cb3907a283deaf69145cf..32c7e63a08f6ca06ae0fb37d4848c9562b371dd8 100644 (file)
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -126,20 +126,17 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
                        }
 
-                       RTLIL::Wire *w_in = new RTLIL::Wire;
-                       w_in->name = genid(cell->name, "", i, "$d");
-                       w_in->width = mem_width;
-                       module->wires[w_in->name] = w_in;
+                       RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
                        data_reg_in.push_back(RTLIL::SigSpec(w_in));
                        c->set("\\D", data_reg_in.back());
 
-                       RTLIL::Wire *w_out = new RTLIL::Wire;
-                       w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
-                       if (module->wires.count(w_out->name) > 0)
-                               w_out->name = genid(cell->name, "", i, "$q");
-                       w_out->width = mem_width;
+                       std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
+                       if (module->wires.count(w_out_name) > 0)
+                               w_out_name = genid(cell->name, "", i, "$q");
+
+                       RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
                        w_out->start_offset = mem_offset;
-                       module->wires[w_out->name] = w_out;
+
                        data_reg_out.push_back(RTLIL::SigSpec(w_out));
                        c->set("\\Q", data_reg_out.back());
                }
@@ -167,10 +164,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                c->set("\\D", rd_addr);
                                count_dff++;
 
-                               RTLIL::Wire *w = new RTLIL::Wire;
-                               w->name = genid(cell->name, "$rdreg", i, "$q");
-                               w->width = mem_abits;
-                               module->wires[w->name] = w;
+                               RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
 
                                c->set("\\Q", RTLIL::SigSpec(w));
                                rd_addr = RTLIL::SigSpec(w);
@@ -184,10 +178,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                c->set("\\Q", rd_signals.back());
                                count_dff++;
 
-                               RTLIL::Wire *w = new RTLIL::Wire;
-                               w->name = genid(cell->name, "$rdreg", i, "$d");
-                               w->width = mem_width;
-                               module->wires[w->name] = w;
+                               RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
 
                                rd_signals.clear();
                                rd_signals.push_back(RTLIL::SigSpec(w));
@@ -207,17 +198,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                c->set("\\S", rd_addr.extract(mem_abits-j-1, 1));
                                count_mux++;
 
-                               RTLIL::Wire *w = new RTLIL::Wire;
-                               w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a");
-                               w->width = mem_width;
-                               module->wires[w->name] = w;
-                               c->set("\\A", RTLIL::SigSpec(w));
-
-                               w = new RTLIL::Wire;
-                               w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b");
-                               w->width = mem_width;
-                               module->wires[w->name] = w;
-                               c->set("\\B", RTLIL::SigSpec(w));
+                               c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
+                               c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
 
                                next_rd_signals.push_back(c->get("\\A"));
                                next_rd_signals.push_back(c->get("\\B"));
@@ -255,9 +237,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                        c->set("\\B", wr_addr);
                        count_wrmux++;
 
-                       RTLIL::Wire *w_seladdr = new RTLIL::Wire;
-                       w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y");
-                       module->wires[w_seladdr->name] = w_seladdr;
+                       RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y"));
                        c->set("\\Y", w_seladdr);
 
                        int wr_offset = 0;
@@ -286,9 +266,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                        c->set("\\A", w);
                                        c->set("\\B", wr_bit);
 
-                                       w = new RTLIL::Wire;
-                                       w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y");
-                                       module->wires[w->name] = w;
+                                       w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
                                        c->set("\\Y", RTLIL::SigSpec(w));
                                }
 
@@ -298,10 +276,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                                c->set("\\B", wr_data.extract(wr_offset, wr_width));
                                c->set("\\S", RTLIL::SigSpec(w));
 
-                               w = new RTLIL::Wire;
-                               w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y");
-                               w->width = wr_width;
-                               module->wires[w->name] = w;
+                               w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
                                c->set("\\Y", w);
 
                                sig.replace(wr_offset, w);

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index e279c02098e58e67882d38a9601bd502f144f150..63d03b20515a1428dbc93653684a974ff5e21e80 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -218,14 +218,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
                }
        }
 
-       std::vector<RTLIL::Wire*> del_wires;
+       std::vector<RTLIL::Wire*> maybe_del_wires;
        for (auto &it : module->wires) {
                RTLIL::Wire *wire = it.second;
                if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) {
                        RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
                        assign_map.apply(s2);
                        if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
-                               del_wires.push_back(wire);
+                               maybe_del_wires.push_back(wire);
                        } else {
                                assert(SIZE(s1) == SIZE(s2));
                                RTLIL::SigSig new_conn;
@@ -242,7 +242,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
                        }
                } else {
                        if (!used_signals.check_any(RTLIL::SigSpec(wire)))
-                               del_wires.push_back(wire);
+                               maybe_del_wires.push_back(wire);
                }
                RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
                if (!used_signals_nodrivers.check_any(sig)) {
@@ -265,6 +265,9 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
                }
        }
 
+
+       std::set<RTLIL::Wire*> del_wires;
+
        int del_wires_count = 0;
        for (auto wire : del_wires)
                if (!used_signals.check_any(RTLIL::SigSpec(wire))) {
@@ -272,11 +275,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
                                log("  removing unused non-port wire %s.\n", wire->name.c_str());
                                del_wires_count++;
                        }
-                       module->wires.erase(wire->name);
-                       count_rm_wires++;
-                       delete wire;
+                       del_wires.insert(wire);
                }
 
+       module->remove(del_wires);
+       count_rm_wires += del_wires.size();;
+
        if (del_wires_count > 0)
                log("  removed %d unused temporary wires.\n", del_wires_count);
 }

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 30e7b748ba8aa560a2111f57dd4bdfb58aff9905..67113a68267c1551cc125d331506dfb04985227f 100644 (file)
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -60,10 +60,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
        std::stringstream sstr;
        sstr << "$procmux$" << (RTLIL::autoidx++);
 
-       RTLIL::Wire *cmp_wire = new RTLIL::Wire;
-       cmp_wire->name = sstr.str() + "_CMP";
-       cmp_wire->width = 0;
-       mod->wires[cmp_wire->name] = cmp_wire;
+       RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
 
        for (auto comp : compare)
        {
@@ -109,10 +106,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
        }
        else
        {
-               ctrl_wire = new RTLIL::Wire;
-               ctrl_wire->name = sstr.str() + "_CTRL";
-               ctrl_wire->width = 1;
-               mod->wires[ctrl_wire->name] = ctrl_wire;
+               ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
 
                // reduce cmp vector to one logic signal
                RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
@@ -147,10 +141,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
        assert(ctrl_sig.size() == 1);
 
        // prepare multiplexer output signal
-       RTLIL::Wire *result_wire = new RTLIL::Wire;
-       result_wire->name = sstr.str() + "_Y";
-       result_wire->width = when_signal.size();
-       mod->wires[result_wire->name] = result_wire;
+       RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
 
        // create the multiplexer itself
        RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 96aa10ba3f84ada78376ef3a43aea7d9b0cb67b1..0c5989b10a15df5556d82cfd52a0ea9959c6ad32 100644 (file)
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -126,11 +126,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
                if (w1->port_input)
                {
-                       RTLIL::Wire *w2 = new RTLIL::Wire;
-                       w2->name = "\\in_" + RTLIL::unescape_id(w1->name);
+                       RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
                        w2->port_input = true;
-                       w2->width = w1->width;
-                       miter_module->add(w2);
 
                        gold_cell->set(w1->name, w2);
                        gate_cell->set(w1->name, w2);
@@ -138,17 +135,11 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
                if (w1->port_output)
                {
-                       RTLIL::Wire *w2_gold = new RTLIL::Wire;
-                       w2_gold->name = "\\gold_" + RTLIL::unescape_id(w1->name);
+                       RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width);
                        w2_gold->port_output = flag_make_outputs;
-                       w2_gold->width = w1->width;
-                       miter_module->add(w2_gold);
 
-                       RTLIL::Wire *w2_gate = new RTLIL::Wire;
-                       w2_gate->name = "\\gate_" + RTLIL::unescape_id(w1->name);
+                       RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
                        w2_gate->port_output = flag_make_outputs;
-                       w2_gate->width = w1->width;
-                       miter_module->add(w2_gate);
 
                        gold_cell->set(w1->name, w2_gold);
                        gate_cell->set(w1->name, w2_gate);
@@ -220,10 +211,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
                        if (flag_make_outcmp)
                        {
-                               RTLIL::Wire *w_cmp = new RTLIL::Wire;
-                               w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name);
+                               RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name));
                                w_cmp->port_output = true;
-                               miter_module->add(w_cmp);
                                miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
                        }
 
@@ -247,10 +236,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
                assert_cell->set("\\EN", RTLIL::SigSpec(1, 1));
        }
 
-       RTLIL::Wire *w_trigger = new RTLIL::Wire;
-       w_trigger->name = "\\trigger";
+       RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
        w_trigger->port_output = true;
-       miter_module->add(w_trigger);
 
        RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
        not_cell->parameters["\\A_WIDTH"] = all_conditions.size();