ARM: Add support for having a TLB cache.

--HG--
extra : rebase_source : 7a5780ab74d7c294682738c7ccb3ce8d56c6fd63

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index bf7577cc758b8ba2ec5237a96d3a9ce7bf85a2f3..665d42af07ff4eb3b5dac2310b70bf6a29cccdf3 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -182,15 +182,16 @@ class BaseCPU(MemObject):
         self.dcache_port = dc.cpu_side
         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
-            if buildEnv['TARGET_ISA'] == 'x86':
-                self.itb_walker_cache = iwc
-                self.dtb_walker_cache = dwc
-                self.itb.walker.port = iwc.cpu_side
-                self.dtb.walker.port = dwc.cpu_side
-                self._cached_ports += ["itb_walker_cache.mem_side", \
-                                       "dtb_walker_cache.mem_side"]
-            elif buildEnv['TARGET_ISA'] == 'arm':
-                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+                if iwc and dwc:
+                    self.itb_walker_cache = iwc
+                    self.dtb_walker_cache = dwc
+                    self.itb.walker.port = iwc.cpu_side
+                    self.dtb.walker.port = dwc.cpu_side
+                    self._cached_ports += ["itb_walker_cache.mem_side", \
+                                           "dtb_walker_cache.mem_side"]
+                else:
+                    self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)