i965: Replace a should-never-happen fallback with asserts where it matters.

We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and
1 more element will get used for gl_VertexID/gl_InstanceID.  So it
should never have been possible to hit this fallback, unless there was
another bug.  If you do hit this, you're probably using gl_VertexID
and falling back to swrast won't work for you anyway.

This also updates the limits for gen6+.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index db0cb1823bd9e84ce10481a5a456a02b94e180e0..52daed8ba58d2a168c65edd61c362fccc18d11a3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -387,17 +387,6 @@ static void brw_prepare_vertices(struct brw_context *brw)
    if (brw->vb.nr_buffers)
       goto prepare;
 
-   /* XXX: In the rare cases where this happens we fallback all
-    * the way to software rasterization, although a tnl fallback
-    * would be sufficient.  I don't know of *any* real world
-    * cases with > 17 vertex attributes enabled, so it probably
-    * isn't an issue at this point.
-    */
-   if (brw->vb.nr_enabled >= BRW_VEP_MAX) {
-      intel->Fallback = true; /* boolean, not bitfield */
-      return;
-   }
-
    for (i = j = 0; i < brw->vb.nr_enabled; i++) {
       struct brw_vertex_element *input = brw->vb.enabled[i];
       const struct gl_client_array *glarray = input->glarray;
@@ -641,6 +630,12 @@ static void brw_emit_vertices(struct brw_context *brw)
     */
 
    if (brw->vb.nr_buffers) {
+      if (intel->gen >= 6) {
+        assert(brw->vb.nr_buffers <= 33);
+      } else {
+        assert(brw->vb.nr_buffers <= 17);
+      }
+
       BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
       for (i = 0; i < brw->vb.nr_buffers; i++) {
@@ -672,6 +667,15 @@ static void brw_emit_vertices(struct brw_context *brw)
       ADVANCE_BATCH();
    }
 
+   /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
+    * for VertexID/InstanceID.
+    */
+   if (intel->gen >= 6) {
+      assert(brw->vb.nr_enabled <= 34);
+   } else {
+      assert(brw->vb.nr_enabled <= 18);
+   }
+
    BEGIN_BATCH(1 + brw->vb.nr_enabled * 2);
    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2*brw->vb.nr_enabled - 1));
    for (i = 0; i < brw->vb.nr_enabled; i++) {

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 85f83187f11f80e094a4b35a37f5c26ec45c0b21..aef56958c66e072ba5e4e261514395c5146fe72e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -881,8 +881,6 @@ struct brw_vertex_element_state
    } ve1;
 };
 
-#define BRW_VEP_MAX 18
-
 struct brw_urb_immediate {
    GLuint opcode:4;
    GLuint offset:6;