Renamed extend_un0() to extend_u0() and use it in genrtlil

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e901a3b52d1d1a0941eaa4fd61507122f55f7d67..c701c2fa061f4e18c3603326bb64b0f610d61c81 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -966,7 +966,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        case AST_TO_UNSIGNED: {
                        RTLIL::SigSpec sig = children[0]->genRTLIL();
                        if (sig.width < width_hint)
-                               sig.extend(width_hint, sign_hint);
+                               sig.extend_u0(width_hint, sign_hint);
                        is_signed = sign_hint;
                        return sig;
        }
@@ -983,7 +983,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                }
                        }
                        if (sig.width < width_hint)
-                               sig.extend(width_hint, false);
+                               sig.extend_u0(width_hint, false);
                        return sig;
                }
 
@@ -998,7 +998,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        for (int i = 0; i < count; i++)
                                sig.append(right);
                        if (sig.width < width_hint)
-                               sig.extend(width_hint, false);
+                               sig.extend_u0(width_hint, false);
                        is_signed = false;
                        return sig;
                }
@@ -1153,7 +1153,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        widthExtend(this, val1, width, is_signed);
                        widthExtend(this, val2, width, is_signed);
 
-                       return mux2rtlil(this, cond, val1, val2);
+                       RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
+
+                       if (sig.width < width_hint)
+                               sig.extend_u0(width_hint, sign_hint);
+                       return sig;
                }
 
        // generate $memrd cells for memory read ports

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4388acb1d7b5b6910493b1cd59490d96d9ab6e6f..d03fb0448529fe7498721339b30d2146e2c9cad7 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -940,7 +940,7 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
        optimize();
 }
 
-void RTLIL::SigSpec::extend_un0(int width, bool is_signed)
+void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 {
        if (this->width > width)
                remove(width, this->width - width);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 376a09abf5a2ee762a227f31ca398b7029f48bdc..7628bf0a8393030d6adfde890986b2f6534c75a8 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -342,7 +342,7 @@ struct RTLIL::SigSpec {
        void append(const RTLIL::SigSpec &signal);
        bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false);
        void extend(int width, bool is_signed = false);
-       void extend_un0(int width, bool is_signed = false);
+       void extend_u0(int width, bool is_signed = false);
        void check() const;
        bool operator <(const RTLIL::SigSpec &other) const;
        bool operator ==(const RTLIL::SigSpec &other) const;

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index f20181f1ebe57cff4ab591929583c87ce1b9b401..b7b361e95097f0f9e9447548d491da887cbfae71 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -151,8 +151,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
                        if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
                                int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
-                               a.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
-                               b.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+                               a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+                               b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
                        }
 
                        RTLIL::SigSpec new_a, new_b;