cores/cpu: revert vexriscv (it seems there is a regression in last version)

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index e8a30b95b9aa1445b5a4a76579a98a0552e2db53..395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit e8a30b95b9aa1445b5a4a76579a98a0552e2db53
+Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5

diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/software/include/base/csr-defs.h
index d98e8dfb7b09cbbd8ba10f7a0e89bf72e60a4ab7..5f5ea84760fb35d095e0cc2794551ad40b98fc8b 100644 (file)
--- a/litex/soc/software/include/base/csr-defs.h
+++ b/litex/soc/software/include/base/csr-defs.h
@@ -3,8 +3,8 @@
 
 #define CSR_MSTATUS_MIE 0x8
 
-#define CSR_IRQ_MASK 0xBC0
-#define CSR_IRQ_PENDING 0xFC0
+#define CSR_IRQ_MASK 0x330
+#define CSR_IRQ_PENDING 0x360
 
 #define CSR_DCACHE_INFO 0xCC0