Match SoC granularity with decoder granularity

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index d086b91a8fa5aed6bb723700b7aae3a266446094..2a96b3d872b423fbebf3f23f68e366f7d87d14a2 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -25,7 +25,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=32)
+        self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8)
 
         tck = 2/(2*2*100e6)
         nphases = 2