radeonsi: set up HTILE in descriptors only when level 0 is accessible

Compression isn't enabled with non-zero levels.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 18b070ba3a22ec801648d58690eb9cdc1a7af7a9..b080562348c540a7be8eaa88af9aa09befa5ccf4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -432,7 +432,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
                        if (sscreen->b.chip_class <= VI)
                                meta_va += base_level_info->dcc_offset;
-               } else if (tex->tc_compatible_htile) {
+               } else if (tex->tc_compatible_htile && first_level == 0) {
                        meta_va = tex->resource.gpu_address + tex->htile_offset;
                }