SimObjects: Clean up handling of C++ namespaces.

Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.

diff --git a/src/SConscript b/src/SConscript
index 09ccf7722b70e4a373e24e78e118a3d66e0fac26..be721d57eaa118f851ddbacd91a612728dc2d9c3 100644 (file)
--- a/src/SConscript
+++ b/src/SConscript
@@ -531,23 +531,24 @@ def buildParams(target, source, env):
                 print >>out, decl
             continue
 
-        code = ''
-        base = obj.get_base()
+        class_path = obj.cxx_class.split('::')
+        class_path.reverse()
+        classname = class_path[0]
+        namespaces = class_path[1:]
 
+        code = ''
         code += '// stop swig from creating/wrapping default ctor/dtor\n'
-        code += '%%nodefault %s;\n' % obj.cxx_class
-        code += 'class %s ' % obj.cxx_class
-        if base:
-            code += ': public %s' % base
+        code += '%%nodefault %s;\n' % classname
+        code += 'class %s ' % classname
+        if obj._base:
+            code += ': public %s' % obj._base.cxx_class
         code += ' {};\n'
 
-        klass = obj.cxx_class;
-        if hasattr(obj, 'cxx_namespace'):
-            new_code = 'namespace %s {\n' % obj.cxx_namespace
+        for ns in namespaces:
+            new_code = 'namespace %s {\n' % ns
             new_code += code
             new_code += '}\n'
             code = new_code
-            klass = '%s::%s' % (obj.cxx_namespace, klass)
 
         print >>out, code
 

diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index fec245b75df0d95155da46c3ffb9d4c070fe35f3..7cfb549f314fca6b61e6dee4b9a27caa3b0ee4e9 100644 (file)
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -35,14 +35,10 @@ class AlphaTLB(SimObject):
 
 class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'AlphaISA::DTB'
     size = 64
 
 class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'AlphaISA::ITB'
     size = 48

diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 1d0244e2249950cf4df9287b477b62b9bf696481..0054acae5a3fd09cc310761a31c82d0259afa335 100644 (file)
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -39,19 +39,16 @@ class MipsTLB(SimObject):
 
 class MipsDTB(MipsTLB):
     type = 'MipsDTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'DTB'
+    cxx_class = 'MipsISA::DTB'
     size = 64
 
 class MipsITB(MipsTLB):
     type = 'MipsITB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'ITB'
+    cxx_class = 'MipsISA::ITB'
     size = 64
 
 class MipsUTB(MipsTLB):
     type = 'MipsUTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'UTB'
+    cxx_class = 'MipsISA::UTB'
     size = 64
 

diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 2d0257cd7a28ede628f2e8752eae6df99304756b..20672a24ea00a4abf0cca4c4a3489fe1c8525807 100644 (file)
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -35,14 +35,10 @@ class SparcTLB(SimObject):
 
 class SparcDTB(SparcTLB):
     type = 'SparcDTB'
-    cxx_namespace = 'SparcISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'SparcISA::DTB'
     size = 64
 
 class SparcITB(SparcTLB):
     type = 'SparcITB'
-    cxx_namespace = 'SparcISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'SparcISA::ITB'
     size = 64

diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 8dd53620e08f241bb2dc8ea54e24b2ac47082a7f..c20566efb6e3d2af8ebd86010af46940bd96dec9 100644 (file)
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -62,8 +62,7 @@ from m5 import build_env
 if build_env['FULL_SYSTEM']:
     class X86PagetableWalker(MemObject):
         type = 'X86PagetableWalker'
-        cxx_namespace = 'X86ISA'
-        cxx_class = 'Walker'
+        cxx_class = 'X86ISA::Walker'
         port = Port("Port for the hardware table walker")
         system = Param.System(Parent.any, "system object")
 
@@ -77,14 +76,10 @@ class X86TLB(SimObject):
 
 class X86DTB(X86TLB):
     type = 'X86DTB'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'X86ISA::DTB'
     size = 64
 
 class X86ITB(X86TLB):
     type = 'X86ITB'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'X86ISA::ITB'
     size = 64

diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py
index e161cd56fb0f949264f0094ccdbb85b263eebe1c..288c253fb92fa039590ebd8d4f65b382c9070758 100644 (file)
--- a/src/arch/x86/bios/E820.py
+++ b/src/arch/x86/bios/E820.py
@@ -58,8 +58,7 @@ from m5.SimObject import SimObject
 
 class X86E820Entry(SimObject):
     type = 'X86E820Entry'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'E820Entry'
+    cxx_class = 'X86ISA::E820Entry'
 
     addr = Param.Addr(0, 'address of the beginning of the region')
     size = Param.MemorySize('0B', 'size of the region')
@@ -67,7 +66,6 @@ class X86E820Entry(SimObject):
 
 class X86E820Table(SimObject):
     type = 'X86E820Table'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'E820Table'
+    cxx_class = 'X86ISA::E820Table'
 
     entries = VectorParam.X86E820Entry([], 'entries for the e820 table')

diff --git a/src/cpu/ExeTracer.py b/src/cpu/ExeTracer.py
index e904f9e7d350ae7705eec121025cfd1b70ed7e08..5754f5d5b2f8f85cc03ea152e88322761084838e 100644 (file)
--- a/src/cpu/ExeTracer.py
+++ b/src/cpu/ExeTracer.py
@@ -32,5 +32,4 @@ from InstTracer import InstTracer
 
 class ExeTracer(InstTracer):
     type = 'ExeTracer'
-    cxx_namespace = 'Trace'
-    cxx_class = 'ExeTracer'
+    cxx_class = 'Trace::ExeTracer'

diff --git a/src/cpu/IntelTrace.py b/src/cpu/IntelTrace.py
index 6e8f567b32809e502c69a88f2af8e465b4eb2a98..3642f3174b7d7beb93859de52ede7be7b6124409 100644 (file)
--- a/src/cpu/IntelTrace.py
+++ b/src/cpu/IntelTrace.py
@@ -32,5 +32,4 @@ from InstTracer import InstTracer
 
 class IntelTrace(InstTracer):
     type = 'IntelTrace'
-    cxx_namespace = 'Trace'
-    cxx_class = 'IntelTrace'
+    cxx_class = 'Trace::IntelTrace'

diff --git a/src/cpu/LegionTrace.py b/src/cpu/LegionTrace.py
index f9b6470a699358ea4974d61d65a61804144a4fde..d450dd00ece36bde49f27c8118680b0e2c5a0d3e 100644 (file)
--- a/src/cpu/LegionTrace.py
+++ b/src/cpu/LegionTrace.py
@@ -32,5 +32,4 @@ from InstTracer import InstTracer
 
 class LegionTrace(InstTracer):
     type = 'LegionTrace'
-    cxx_namespace = 'Trace'
-    cxx_class = 'LegionTrace'
+    cxx_class = 'Trace::LegionTrace'

diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py
index 96b4e991b079f085a99989b71be9466f83495f96..f410b54734f9cc192f8dee637d922685fb63172c 100644 (file)
--- a/src/cpu/NativeTrace.py
+++ b/src/cpu/NativeTrace.py
@@ -32,5 +32,4 @@ from InstTracer import InstTracer
 
 class NativeTrace(InstTracer):
     type = 'NativeTrace'
-    cxx_namespace = 'Trace'
-    cxx_class = 'NativeTrace'
+    cxx_class = 'Trace::NativeTrace'

diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index cf513b834a2f832d15b10518312139ebd19dfa9e..5821a3e96febb32c4b8060e39db512780a9cf479 100644 (file)
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -160,8 +160,7 @@ class NSGigE(EtherDevBase):
 
 class Sinic(EtherDevBase):
     type = 'Sinic'
-    cxx_namespace = 'Sinic'
-    cxx_class = 'Device'
+    cxx_class = 'Sinic::Device'
 
     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 64f4ec5af24b251741d7f3ce88b71f7112d6c988..ac81582f35508da1e1b96b4156b030b418031c14 100644 (file)
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -123,7 +123,6 @@ instanceDict = {}
 class MetaSimObject(type):
     # Attributes that can be set only at initialization time
     init_keywords = { 'abstract' : types.BooleanType,
-                      'cxx_namespace' : types.StringType,
                       'cxx_class' : types.StringType,
                       'cxx_type' : types.StringType,
                       'cxx_predecls' : types.ListType,
@@ -190,36 +189,31 @@ class MetaSimObject(type):
         # the following is not true is when we define the SimObject
         # class itself (in which case the multidicts have no parent).
         if isinstance(base, MetaSimObject):
+            cls._base = base
             cls._params.parent = base._params
             cls._ports.parent = base._ports
             cls._values.parent = base._values
             cls._port_refs.parent = base._port_refs
             # mark base as having been subclassed
             base._instantiated = True
+        else:
+            cls._base = None
 
         # default keyword values
         if 'type' in cls._value_dict:
-            _type = cls._value_dict['type']
             if 'cxx_class' not in cls._value_dict:
-                cls._value_dict['cxx_class'] = _type
+                cls._value_dict['cxx_class'] = cls._value_dict['type']
 
-            namespace = cls._value_dict.get('cxx_namespace', None)
-
-            _cxx_class = cls._value_dict['cxx_class']
-            if 'cxx_type' not in cls._value_dict:
-                t = _cxx_class + '*'
-                if namespace:
-                    t = '%s::%s' % (namespace, t)
-                cls._value_dict['cxx_type'] = t
+            cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class']
+                
             if 'cxx_predecls' not in cls._value_dict:
                 # A forward class declaration is sufficient since we are
                 # just declaring a pointer.
-                decl = 'class %s;' % _cxx_class
-                if namespace:
-                    namespaces = namespace.split('::')
-                    namespaces.reverse()
-                    for namespace in namespaces:
-                        decl = 'namespace %s { %s }' % (namespace, decl)
+                class_path = cls._value_dict['cxx_class'].split('::')
+                class_path.reverse()
+                decl = 'class %s;' % class_path[0]
+                for ns in class_path[1:]:
+                    decl = 'namespace %s { %s }' % (ns, decl)
                 cls._value_dict['cxx_predecls'] = [decl]
 
             if 'swig_predecls' not in cls._value_dict:
@@ -351,12 +345,6 @@ class MetaSimObject(type):
     def __str__(cls):
         return cls.__name__
 
-    def get_base(cls):
-        if str(cls) == 'SimObject':
-            return None
-
-        return  cls.__bases__[0].type
-
     def cxx_decl(cls):
         code = "#ifndef __PARAMS__%s\n" % cls
         code += "#define __PARAMS__%s\n\n" % cls
@@ -387,16 +375,15 @@ class MetaSimObject(type):
         code += "\n".join(predecls2)
         code += "\n\n";
 
-        base = cls.get_base()
-        if base:
-            code += '#include "params/%s.hh"\n\n' % base
+        if cls._base:
+            code += '#include "params/%s.hh"\n\n' % cls._base.type
 
         for ptype in ptypes:
             if issubclass(ptype, Enum):
                 code += '#include "enums/%s.hh"\n' % ptype.__name__
                 code += "\n\n"
 
-        code += cls.cxx_struct(base, params)
+        code += cls.cxx_struct(cls._base, params)
 
         # close #ifndef __PARAMS__* guard
         code += "\n#endif\n"
@@ -409,7 +396,7 @@ class MetaSimObject(type):
         # now generate the actual param struct
         code = "struct %sParams" % cls
         if base:
-            code += " : public %sParams" % base
+            code += " : public %sParams" % base.type
         code += "\n{\n"
         if not hasattr(cls, 'abstract') or not cls.abstract:
             if 'type' in cls.__dict__:
@@ -421,24 +408,7 @@ class MetaSimObject(type):
 
         return code
 
-    def cxx_type_decl(cls):
-        base = cls.get_base()
-        code = ''
-
-        if base:
-            code += '#include "%s_type.h"\n' % base
-
-        # now generate dummy code for inheritance
-        code += "struct %s" % cls.cxx_class
-        if base:
-            code += " : public %s" % base.cxx_class
-        code += "\n{};\n"
-
-        return code
-
     def swig_decl(cls):
-        base = cls.get_base()
-
         code = '%%module %s\n' % cls
 
         code += '%{\n'
@@ -466,8 +436,8 @@ class MetaSimObject(type):
         code += "\n".join(predecls2)
         code += "\n\n";
 
-        if base:
-            code += '%%import "params/%s.i"\n\n' % base
+        if cls._base:
+            code += '%%import "params/%s.i"\n\n' % cls._base.type
 
         for ptype in ptypes:
             if issubclass(ptype, Enum):

diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py
index f7500f1e8417aa12cd7a978bc438fedebe56a989..9ba91a019b7767781bbdfa52b51763b409305e56 100644 (file)
--- a/src/sim/InstTracer.py
+++ b/src/sim/InstTracer.py
@@ -31,5 +31,5 @@ from m5.params import *
 
 class InstTracer(SimObject):
     type = 'InstTracer'
-    cxx_namespace = 'Trace'
+    cxx_class = 'Trace::InstTracer'
     abstract = True