[xcc,opcodes,pk,sim] cleanup to FP ISA

- Added 5th rounding mode
- Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...)
- merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode
- made MFFL.D and MFFH.D illegal in RV64

diff --git a/riscv/decode.h b/riscv/decode.h
index 6360ab8687dcf81e9bcfe977e20df1e2be36ba16..4c30e623e9684617b88d7b4dbaa7712de355ef56 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -181,6 +181,7 @@ private:
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define xpr64 (xprlen == 64)
 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
+#define require_xpr32 if(xpr64) throw trap_illegal_instruction
 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 #define set_fp_exceptions ({ set_fsr(fsr | \

diff --git a/riscv/execute.h b/riscv/execute.h
index 844745d786cc83e20cd88e7b38749dd4dd5927a6..ff79cafdd842d41ae225f5380f6b637d5304ee81 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -174,20 +174,6 @@ switch((insn.bits >> 0x0) & 0x7f)
         }
         #include "insns/unimp.h"
       }
-      case 0x1:
-      {
-        if((insn.bits & 0x7c1ffff) == 0x97)
-        {
-          #include "insns/mfcr.h"
-          break;
-        }
-        if((insn.bits & 0xf801ffff) == 0x497)
-        {
-          #include "insns/mtcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       case 0x2:
       {
         if((insn.bits & 0xffffffff) == 0x117)
@@ -705,16 +691,6 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0x1ffff) == 0x6053)
-        {
-          #include "insns/fsinjn_s.h"
-          break;
-        }
-        if((insn.bits & 0x7c1ffff) == 0x18453)
-        {
-          #include "insns/mff_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0x11053)
         {
           #include "insns/fcvt_s_d.h"
@@ -740,51 +716,26 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fcvt_l_s.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1c453)
-        {
-          #include "insns/mtf_s.h"
-          break;
-        }
         if((insn.bits & 0x1f1ff) == 0x3053)
         {
           #include "insns/fdiv_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x16053)
-        {
-          #include "insns/fc_lt_s.h"
-          break;
-        }
         if((insn.bits & 0x1f1ff) == 0x2053)
         {
           #include "insns/fmul_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x7053)
-        {
-          #include "insns/fsmul_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0xa053)
         {
           #include "insns/fcvt_w_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x5053)
-        {
-          #include "insns/fsinj_s.h"
-          break;
-        }
         if((insn.bits & 0x1f1ff) == 0x1053)
         {
           #include "insns/fsub_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x17053)
-        {
-          #include "insns/fc_le_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0xf053)
         {
           #include "insns/fcvtu_s_w.h"
@@ -810,142 +761,186 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fsqrt_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x15053)
-        {
-          #include "insns/fc_eq_s.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
       case 0x1:
       {
-        if((insn.bits & 0x7c1ffff) == 0x184d3)
+        if((insn.bits & 0x3ff1ff) == 0xc0d3)
         {
-          #include "insns/mff_d.h"
+          #include "insns/fcvt_d_l.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x60d3)
+        if((insn.bits & 0x3ff1ff) == 0x80d3)
         {
-          #include "insns/fsinjn_d.h"
+          #include "insns/fcvt_l_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xc0d3)
+        if((insn.bits & 0x1f1ff) == 0x20d3)
         {
-          #include "insns/fcvt_d_l.h"
+          #include "insns/fmul_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xe0d3)
+        if((insn.bits & 0x3ff1ff) == 0xa0d3)
         {
-          #include "insns/fcvt_d_w.h"
+          #include "insns/fcvt_w_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x100d3)
+        if((insn.bits & 0x3ff1ff) == 0xb0d3)
         {
-          #include "insns/fcvt_d_s.h"
+          #include "insns/fcvtu_w_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x194d3)
+        if((insn.bits & 0x1f1ff) == 0xd3)
         {
-          #include "insns/mffl_d.h"
+          #include "insns/fadd_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x1a4d3)
+        if((insn.bits & 0x3ff1ff) == 0x90d3)
         {
-          #include "insns/mffh_d.h"
+          #include "insns/fcvtu_l_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x80d3)
+        if((insn.bits & 0x1f1ff) == 0x10d3)
         {
-          #include "insns/fcvt_l_d.h"
+          #include "insns/fsub_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xf0d3)
+        if((insn.bits & 0x3ff1ff) == 0x40d3)
         {
-          #include "insns/fcvtu_d_w.h"
+          #include "insns/fsqrt_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x160d3)
+        if((insn.bits & 0x1f1ff) == 0x30d3)
         {
-          #include "insns/fc_lt_d.h"
+          #include "insns/fdiv_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x20d3)
+        if((insn.bits & 0x3ff1ff) == 0xd0d3)
         {
-          #include "insns/fmul_d.h"
+          #include "insns/fcvtu_d_l.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x150d3)
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0x1ffff) == 0x6e53)
         {
-          #include "insns/fc_eq_d.h"
+          #include "insns/fsinjn_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x70d3)
+        if((insn.bits & 0x7c1ffff) == 0x18e53)
         {
-          #include "insns/fsmul_d.h"
+          #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x50d3)
+        if((insn.bits & 0xf83fffff) == 0x1de53)
         {
-          #include "insns/fsinj_d.h"
+          #include "insns/mtfsr.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa0d3)
+        if((insn.bits & 0x3fffff) == 0x1ce53)
         {
-          #include "insns/fcvt_w_d.h"
+          #include "insns/mtf_s.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1c4d3)
+        if((insn.bits & 0x7ffffff) == 0x1be53)
         {
-          #include "insns/mtf_d.h"
+          #include "insns/mffsr.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x170d3)
+        if((insn.bits & 0x1ffff) == 0x16e53)
         {
-          #include "insns/fc_le_d.h"
+          #include "insns/fc_lt_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb0d3)
+        if((insn.bits & 0x1ffff) == 0x7e53)
         {
-          #include "insns/fcvtu_w_d.h"
+          #include "insns/fsmul_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0xd3)
+        if((insn.bits & 0x1ffff) == 0x5e53)
         {
-          #include "insns/fadd_d.h"
+          #include "insns/fsinj_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x90d3)
+        if((insn.bits & 0x1ffff) == 0x17e53)
         {
-          #include "insns/fcvtu_l_d.h"
+          #include "insns/fc_le_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x10d3)
+        if((insn.bits & 0x1ffff) == 0x15e53)
         {
-          #include "insns/fsub_d.h"
+          #include "insns/fc_eq_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x40d3)
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0x7c1ffff) == 0x18ed3)
         {
-          #include "insns/fsqrt_d.h"
+          #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x30d3)
+        if((insn.bits & 0x1ffff) == 0x6ed3)
         {
-          #include "insns/fdiv_d.h"
+          #include "insns/fsinjn_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd0d3)
+        if((insn.bits & 0x3fffff) == 0xeed3)
         {
-          #include "insns/fcvtu_d_l.h"
+          #include "insns/fcvt_d_w.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x5:
-      {
-        if((insn.bits & 0x1ffff) == 0x1c6d3)
+        if((insn.bits & 0x3fffff) == 0x10ed3)
+        {
+          #include "insns/fcvt_d_s.h"
+          break;
+        }
+        if((insn.bits & 0x7c1ffff) == 0x19ed3)
+        {
+          #include "insns/mffl_d.h"
+          break;
+        }
+        if((insn.bits & 0x7c1ffff) == 0x1aed3)
         {
-          #include "insns/mtflh_d.h"
+          #include "insns/mffh_d.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1ced3)
+        {
+          #include "insns/mtf_d.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0xfed3)
+        {
+          #include "insns/fcvtu_d_w.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x16ed3)
+        {
+          #include "insns/fc_lt_d.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x15ed3)
+        {
+          #include "insns/fc_eq_d.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x7ed3)
+        {
+          #include "insns/fsmul_d.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x5ed3)
+        {
+          #include "insns/fsinj_d.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x17ed3)
+        {
+          #include "insns/fc_le_d.h"
           break;
         }
         #include "insns/unimp.h"

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
deleted file mode 100644 (file)
index f3bd81e..0000000
--- a/riscv/insns/mfcr.h
+++ /dev/null
@@ -1,18 +0,0 @@
-reg_t val;
-
-switch(insn.rtype.rs2)
-{
-  case 0:
-    require_fp;
-    val = fsr;
-    break;
-
-  case 1:
-    val = 32; // synci_step
-    break;
-
-  default:
-    val = -1;
-}
-
-RD = sext_xprlen(val);

diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h
index 78b5423880b9be456467d4c3d3e9bba1b02646ea..02a94fa9f3c551da023a052c3f75ab6b8de49c73 100644 (file)
--- a/riscv/insns/mffh_d.h
+++ b/riscv/insns/mffh_d.h
@@ -1,2 +1,3 @@
+require_xpr32;
 require_fp;
 RD = sext32(FRS2 >> 32);

diff --git a/riscv/insns/mffl_d.h b/riscv/insns/mffl_d.h
index 589b33b7d769d45f8a873e2308dbdf131339eac6..55e99fc9ac3e536761f814b60f646da1ac18e82b 100644 (file)
--- a/riscv/insns/mffl_d.h
+++ b/riscv/insns/mffl_d.h
@@ -1,2 +1,3 @@
+require_xpr32;
 require_fp;
 RD = sext32(FRS2);

diff --git a/riscv/insns/mffsr.h b/riscv/insns/mffsr.h
new file mode 100644 (file)
index 0000000..29debc4
--- /dev/null
+++ b/riscv/insns/mffsr.h
@@ -0,0 +1,2 @@
+require_fp;
+RD = fsr;

diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
deleted file mode 100644 (file)
index 22cd4d5..0000000
--- a/riscv/insns/mtcr.h
+++ /dev/null
@@ -1,7 +0,0 @@
-switch(insn.rtype.rs2)
-{
-  case 0:
-    require_fp;
-    set_fsr(RS1);
-    break;
-}

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 29792ec425b41048e960568fc37f712dcc13eeae..b03697b1bc276b7f21b9998a3583c7807c7548f0 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,5 @@
-require_xpr64;
 require_fp;
-FRD = RS1;
+if(xpr64)
+  FRD = RS1;
+else
+  FRD = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);

diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h
deleted file mode 100644 (file)
index ed4014e..0000000
--- a/riscv/insns/mtflh_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);

diff --git a/riscv/insns/mtfsr.h b/riscv/insns/mtfsr.h
new file mode 100644 (file)
index 0000000..23ee2bd
--- /dev/null
+++ b/riscv/insns/mtfsr.h
@@ -0,0 +1,2 @@
+require_fp;
+set_fsr(RS1);