Merge remote-tracking branch 'origin/master' into xaig_dff

diff --cc techlibs/xilinx/cells_sim.v
index ef963793c9691eb59f96091f60525ef63e0ca610,cf7923777ce8dd37216fd0fdade3b9a2fae49b14..7941a94cd5dda6f87a21dc9297035aa82745e178
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -312,15 -310,60 +312,50 @@@ module FDRE_1 
    (* abc9_arrival=303 *)
    output reg Q,
    (* clkbuf_sink *)
 -  (* invertible_pin = "IS_C_INVERTED" *)
    input C,
 -  input CE,
 -  (* invertible_pin = "IS_D_INVERTED" *)
 -  input D,
 -  (* invertible_pin = "IS_S_INVERTED" *)
 -  input S
 +  input CE, D, R
  );
 -  parameter [0:0] INIT = 1'b1;
 -  parameter [0:0] IS_C_INVERTED = 1'b0;
 -  parameter [0:0] IS_D_INVERTED = 1'b0;
 -  parameter [0:0] IS_S_INVERTED = 1'b0;
 +  parameter [0:0] INIT = 1'b0;
    initial Q <= INIT;
 -  generate case (|IS_C_INVERTED)
 -    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -  endcase endgenerate
 +  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
  endmodule
  
+ module FDRSE (
+   output reg Q,
+   (* clkbuf_sink *)
+   (* invertible_pin = "IS_C_INVERTED" *)
+   input C,
+   (* invertible_pin = "IS_CE_INVERTED" *)
+   input CE,
+   (* invertible_pin = "IS_D_INVERTED" *)
+   input D,
+   (* invertible_pin = "IS_R_INVERTED" *)
+   input R,
+   (* invertible_pin = "IS_S_INVERTED" *)
+   input S
+ );
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_C_INVERTED = 1'b0;
+   parameter [0:0] IS_CE_INVERTED = 1'b0;
+   parameter [0:0] IS_D_INVERTED = 1'b0;
+   parameter [0:0] IS_R_INVERTED = 1'b0;
+   parameter [0:0] IS_S_INVERTED = 1'b0;
+   initial Q <= INIT;
+   wire c = C ^ IS_C_INVERTED;
+   wire ce = CE ^ IS_CE_INVERTED;
+   wire d = D ^ IS_D_INVERTED;
+   wire r = R ^ IS_R_INVERTED;
+   wire s = S ^ IS_S_INVERTED;
+   always @(posedge c)
+     if (r)
+       Q <= 0;
+     else if (s)
+       Q <= 1;
+     else if (ce)
+       Q <= d;
+ endmodule
+ 
 +(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
  module FDCE (
    (* abc9_arrival=303 *)
    output reg Q,

diff --cc techlibs/xilinx/synth_xilinx.cc
index de262c8adaa36992ffb244a439007d29128e52df,971089b289a385230718a3ff02de4d14560a78a0..ac6fedc58596c2338bcbb4214062ca5360e7b18b
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -559,10 -564,14 +566,11 @@@ struct SynthXilinxPass : public ScriptP
                                run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
                        std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
                        if (help_mode)
 -                              techmap_args += " [-map " + ff_map_file + "]";
 -                      else if (abc9)
 -                              techmap_args += " -map +/xilinx/abc9_unmap.v";
 -                      else
 -                              techmap_args += " -map " + ff_map_file;
 -                      run("techmap " + techmap_args);
 +                              techmap_args += stringf("[-map %s]", ff_map_file.c_str());
 +                      else if (!abc9)
 +                              techmap_args += stringf(" -map %s", ff_map_file.c_str());
 +                      run("techmap " + techmap_args, "(option without '-abc9')");
+                       run("xilinx_dffopt");
 -                      run("clean");
                }
  
                if (check_label("finalize")) {