i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.

On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
region, but on IVB and BYT DF regions must be programmed in terms of
floats. A <0,2,1> region accomplishes this.

v2:
- Apply region <0,2,1> in brw_reg_from_fs_reg() (Curro).

v3:
- Added comment explaining the reason (Curro).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index bcb6608d3aeb36dd4769aef0027fa4175667d816..bc15fd11d960d0406bfec5fec50130ca540f8775 100644 (file)
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -143,6 +143,19 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
       unreachable("not reached");
    }
 
+   /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
+    * region, but on IVB and BYT DF regions must be programmed in terms of
+    * floats. A <0,2,1> region accomplishes this.
+    */
+   if (devinfo->gen == 7 && !devinfo->is_haswell &&
+       type_sz(reg->type) == 8 &&
+       brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
+       brw_reg.width == BRW_WIDTH_1 &&
+       brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
+      brw_reg.width = BRW_WIDTH_2;
+      brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1;
+   }
+
    return brw_reg;
 }