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 # Cole Poirier
 
+Apprentice and assistant Project coordinator for Libre-SOC
+
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=325>
+# Status tracking
+
+move things along from one stage to the next
 
-* Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401> (see also [Bug #397](https://bugs.libre-soc.org/show_bug.cgi?id=397))
+## Currently working on
 
-List of things that need more fleshed out bug reports:
+- Recruiting more engineers to the project <https://bugs.libre-soc.org/show_bug.cgi?id=375> <https://bugs.libre-soc.org/show_bug.cgi?id=380> and make wiki pages(s) for this purpose <https://bugs.libre-soc.org/show_bug.cgi?id=379>
 
+- Bperm tutorial <https://bugs.libre-soc.org/show_bug.cgi?id=388>
 
-* Memory bus/L1/L2 Cache documentation <https://bugs.libre-soc.org/show_bug.cgi?id=397>
+- Create a bug report for each diagram to be converted to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=389>
 
-* Bperm tutorial
+- Reach out to developers of 'BlackParrot' RV64GC Multicore SoC <https://bugs.libre-soc.org/show_bug.cgi?id=394>
 
-* Bugseverywhere, need specific bug report for discussing new bug tracker and migration (or also <https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go>)
+- Convert comp_unit_req_rel diagram to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=442>
 
-* Competition to LS: Skywater 130nm production-ready PDK gets opensourced (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html>)
+## List of things that need more fleshed out bug reports:
 
 * Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
 
 * LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
 
-* Follow up with graphics engineers, esp ones Yehowshua has already reached out to (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html>)
+## Completed but not yet submitted
+
+- Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401>
+
+- Coriolis2 documentation and setup scripts
+  <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  <https://bugs.libre-soc.org/show_bug.cgi?id=320>
+  <https://bugs.libre-soc.org/show_bug.cgi?id=404>
+  <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+
+## Submitted for NLNet RFP
+
+submitted but not confirmed paid:
+
+### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
+
+## Paid