Pl011: Added registers UART_RSR/UART_ECR

UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4).  As
these transmission errors never occur, they are implemented as RAZ/WI.

Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.

Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index e47cc6753dc006ac75d95d364e32f7406ef852f4..5ca9f608739d0e0be05f7563ba965535ade31adf 100644 (file)
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -92,6 +92,9 @@ Pl011::read(PacketPtr pkt)
             }
         }
         break;
+      case UART_RSR:
+        data = 0x0; // We never have errors
+        break;
       case UART_FR:
         data =
             UART_FR_CTS | // Clear To Send
@@ -205,6 +208,8 @@ Pl011::write(PacketPtr pkt)
         clearInterrupts(UART_TXINTR);
         raiseInterrupts(UART_TXINTR);
         break;
+      case UART_ECR: // clears errors, ignore
+        break;
       case UART_CR:
         control = data;
         break;

diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index 2317b31142bc67f7b56d597ccabb8ab38b43c10d..5a92d8890c50745e8f443c095985a3320cb51364 100644 (file)
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -118,6 +118,8 @@ class Pl011 : public Uart, public AmbaDevice
   protected: // Registers
     static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
     static const int UART_DR = 0x000;
+    static const int UART_RSR = 0x004;
+    static const int UART_ECR = 0x004;
     static const int UART_FR = 0x018;
     static const int UART_FR_CTS  = 0x001;
     static const int UART_FR_RXFE = 0x010;