do not use wide luts in testcase

diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index d612e4eaa966f37550f2fa0c9dc88638da086147..1cb3d53e607a4a44d7ac294e94b57c370e36450f 100644 (file)
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
@@ -27,7 +27,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 5 t:LUT4
@@ -39,7 +39,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 10 t:LUT4